*SRE

34980A

*SRE

Syntax

*SRE <enable_value>

*SRE?

Description

This command enables bits in the enable register for the Status Byte Register group. Once enabled, the corresponding bits may generate a Request for Service (RQS) in the Status Byte. This RQS event may generate a "call back" to your application as a type of asynchronous interrupt.

For more information on the SCPI Status System for the Agilent 34980A, see Status System Introduction.

Parameters

Name

Type

Range of Values

Default Value

<enable_value>

Numeric

A decimal value which corresponds to the binary-weighted sum of the bits in the register (see table below).

This is a required parameter

Remarks

  • The following table lists the bit definitions for the Status Byte Register.

Bit Number

Decimal Value

Definition

0  Module Event Summary

1

One of more bits are set in the Module Event Register (bits must be enabled, see STATus:MODule:ENABle command).

1  Alarm Condition

2

One or more bits are set in the Alarm Register (bits must be enabled, see STATus:ALARm:ENABle command).

2  Error Queue

4

One or more errors have been stored in the Error Queue. Use the SYSTem:ERRor? command to read and delete errors.

3  Questionable Data Summary

8

One or more bits are set in the Questionable Data Register (bits must be enabled, see STATus:QUEStionable:ENABle command).

4  Message Available

16

Data is available in the instrument's output buffer.

5  Standard Event Summary

32

One or more bits are set in the Standard Event Register (bits must be enabled, see *ESE command).

6  Master Summary

64

One or more bits are set in the Status Byte Register and may generate a Request for Service (RQS). Bits must be enabled using the *SRE command.

7  Standard Operation Summary

128

One or more bits are set in the Standard Operation Register (bits must be enabled, see STATus:OPERation:ENABle command).

  • Use the <enable_value> parameter to specify which bits will be enabled. The decimal value specified corresponds to the binary-weighted sum of the bits you wish to enable in the register. For example, to enable bit 1 (decimal value = 2), bit 3 (decimal value = 8), and bit 6 (decimal value = 64), the corresponding decimal value would be 74 (2 + 8 + 64).

  • A STATus:PRESet command does not clear the bits in the Status Byte enable register.

  • The Status Byte enable register is cleared when you execute the *SRE 0 command.

Return Format

The query command reads the enable register and returns a decimal value which corresponds to the binary-weighted sum of all bits set in the register. For example, if bit 3 (decimal value = 8) and bit 7 (decimal value = 128) are enabled, the query command will return "+136".

Examples

The following command enables bit 4 (decimal value = 16) in the enable register.

*SRE 16

The following query returns which bits are enabled in the register.  

*SRE?

Typical Response:  +16

See Also

*STB?