SOURce:DIGital:MEMory:ENABle
Syntax
SOURce:DIGital:MEMory:ENABle <mode>, (@<ch_list>)
SOURce:DIGital:MEMory:ENABle? (@<ch_list>)
Description
This command enables buffered (memory) output operations on the 34950A Digital I/O Module and places the specified channels in the wait-for-trigger state. The width of the first channel in each bank (i.e., channels 101 and 201) controls the width of the memory operations (64K x 8 Bits, 64K x 16 Bits, or 32K x 32 Bits). The first channel on the specified bank must be configured as an output prior to starting a buffered write (see SOURce:DIGital:DATA[:<width>] command) and a trace must be downloaded to memory and assigned to the specified bank (see SOURce:DIGital:MEMory:TRACe command).
Used With:
34950A Digital I/O Module
Parameters
|
Name |
Type |
Range of Values |
Default Value |
|
<mode> |
Boolean |
{OFF|0|ON|1} |
OFF (disabled) |
|
<ch_list> |
Numeric |
The first channel on a bank in the form (@sccc).
|
This is a required parameter |
Remarks
Depending on the width specified (see SOURce:DIGital:DATA[:<width>] command), the channel numbering is modified as shown below. For example, if you specify the width as a 16-bit WORD, channels 101 and 102 are combined and addressed collectively as channel 101.
|
|
Bank 2 |
Bank 1 |
||||||
|
BYTE (8 Bits): |
Ch 204 |
Ch 203 |
Ch 202 |
Ch 201 |
Ch 104 |
Ch 103 |
Ch 102 |
Ch 101 |
|
WORD (16 Bits): |
Ch 203 |
Ch 201 |
Ch 103 |
Ch 101 |
||||
|
LWORd (32 Bits): |
Ch 201 |
Ch 101 |
||||||
Once memory is enabled, send the SOURce:DIGital:MEMory:STARt or SOURce:DIGital:MEMory:STEP command to start the buffered write. You can also start a buffered write operation using the hardware INTR (interrupt) line as an input to the module (see SOURce:DIGital:INTerrupt[:ENABle] command).
If memory is currently disabled, sending the SOURce:DIGital:MEMory:STARt command will enable memory and start the buffered write.
Changing the direction will disable buffered operations on the specified digital channels. In addition, changing the channel width will disable buffered operations and clear memory on the specified digital channels.
The instrument disables buffered memory after a Factory Reset (*RST command). An Instrument Preset (SYSTem:PRESet command) or Card Reset (SYSTem:CPON command) does not change the setting.
Return Format
The query command returns "0" (OFF) or "1" (ON) for each channel specified. Multiple responses are separated by commas.
Examples
The following program segment downloads and outputs a "walking ones" pattern from channel 101 on the module in slot 3. The length of the trace is set to 32 samples. In addition, the cycle count is set to output the complete trace three times. Once memory is enabled, a software trigger is used to trigger the memory output.
SOUR:DIG:DATA:WORD
#HFFFF,(@3101) !Set
initial output pattern
SOUR:DIG:MEM:NCYC 3,(@3101) !Output
complete trace 3 times
TRAC:DIG:FUNC (@3101),WONES,PATTERN_1,32 !Download
"walking ones" pattern
SOUR:DIG:MEM:TRAC PATTERN_1,(@3101) !Assign
trace to channel 101
SOUR:DIG:MEM:ENAB ON,(@3101) !Enable
memory on channel 101
SOUR:DIG:MEM:START (@3101) !Trigger
memory output
The following program segment enables inputs to the INTR line on channels 101 and 201 in slot 3. The output will start when a rising edge is detected on the INTR line.
CONF:DIG:WIDTH
WORD,(@3101,3201) !Width
= 16 bits
SOUR:DIG:MEM:ENAB ON,(@3101,3201) !Enable
memory on channels 101 and 201
SOUR:DIG:INT:MODE START,(@3101,3201) !Output
starts on rising edge
SOUR:DIG:INT:ENAB ON,(@3101,3201) !Enable
interrupt input
The following query returns the memory setting.
SOUR:DIG:MEM:ENAB? (@3101,3201)
Typical Response: 1,1
See Also
CONFigure:DIGital:HANDshake:SYNChronous:STRobe[:SOURce]
SOURce:DIGital:INTerrupt[:ENABle]
SOURce:DIGital:MEMory:NCYCles
SOURce:DIGital:MEMory:STARt
SOURce:DIGital:MEMory:TRACe