Dynamic Generation Clock Sources

Dynamic generation is a clocked operation. The dynamic generation operation is clocked by one of several clocking resources. Your application needs may determine which source you should use. Refer to the main Clocking diagram to see a block diagram for these clock resources.

The following information discusses additional considerations for using these clocking resources for dynamic generation:

• On Board Clock

  The default clock source for dynamic generation sessions is the On Board Clock. This clock can be locked to a reference clock to synchronize operations across multiple devices or can be used without a reference clock when multidevice synchronization is not required. The On Board Clock is derived from integer divisors of the 200 MHz VCXO. Refer to the NI 655x specifications for information about the possible On Board Clock frequencies.

  You can configure the On Board Clock source in the following ways:

  • Free-running, nonphase-locked—In this mode, the VCXO is used at its fundamental frequency, allowing for a stable and accurate 200 MHz clock. This configuration is the default setting, and it is most useful when only one NI 655x is in the system or when multidevice synchronization is not required.
  • Phase-Locked—The On Board Clock source can be locked to a reference clock using the PLL circuit to ensure that Sample clock alignment across devices is achieved. In this operation mode, the PLL circuit must be provided a precision source to which it can lock. The On Board Clock source can be locked to one of the following reference clock sources:
    • PXI_CLK10 (NI PXI-6551/6552 only)/RTSI 7 (NI PCI-6551/6552)—The PXI standard defines a precision 10 MHz reference (PXI_CLK10) to be distributed across the backplane to each device in the PXI chassis. If you are using PXI, this 10 MHz backplane clock is used as the reference for the PLL in this mode of PLL operation. If you are using PCI, drive the 10 MHz On Board Reference Clock onto RTSI 7, and configure RTSI 7 as the reference clock source.
    • CLK IN—If you want to provide your own reference, you can provide an external source on the CLK IN SMB connector to which the PLL can lock. Using an external reference allows you to easily synchronize clocks across instruments within and outside of the system. Refer to the NI 655x specifications for information about the possible reference clock frequencies.
• External Source (CLK IN)

  Alternatively, your dynamic generation operation can be driven from an external Sample clock source. Using an external frequency generator, you can drive dynamic generation operations at any frequency within the NI 655x specifications. Frequency limitations and acquisition levels are listed in NI 655x specifications.

• PXI_STAR (NI PXI-6551/6552 only)

  The PXI specification allocates resources for high-speed precision clock and trigger routing across the PXI backplane. The NI PXI-655x can use this resource to clock your dynamic generation task. An external source can drive this resource at any suitable frequency, allowing the NI PXI-655x to operate at noninteger divisors of 200 MHz, similar to how it operates using an external clock source (CLK IN).

For a summary of these and other clock sources, refer to Clock Sources Summary.