NIHSDIO_ATTR_DIGITAL_LEVEL_PAUSE_TRIGGER_POSITION
Specific Attribute
| Data type |
Access | Applies to | Coercion | High-Level Functions |
|---|---|---|---|---|
| ViInt32 | R/W | N/A | None | None |
Specifies the position where the digital level Pause trigger is asserted, relative to the Sample clock. Trigger voltages and positions are only relevant if the trigger source is a front panel connector.
Defined Values:
| NIHSDIO_VAL_SAMPLE_CLOCK_RISING_EDGE (18) | The trigger is received synchronously with the rising edge of the Sample clock. |
| NIHSDIO_VAL_SAMPLE_CLOCK_FALLING_EDGE (19) | The trigger is received synchronously with the Sample clock falling edge. |
| NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE (20) | The trigger is received synchronously with the delay the Sample clock rising edge. You can use this value when the Sample clock rate is 25 MS/s or more. Specify the delay using NIHSDIO_ATTR_DATA_POSITION_DELAY. This choice has more jitter than the rising or falling edge values. Certain devices have Sample clock frequency limitations on when a custom delay can be used. Refer to the device sections for details. |