Voltage Ranges and Settings
The NI 656x uses the following three voltage logic families on various pins:
- LVDS—Data channels, PFI<1..3>, clock inputs/outputs
- LVPECL—Exported Sample clock
- 3.3V Logic/TTL/CMOS—PFI 0, PFI 3
All data channels on NI 656x devices are LVDS compliant. The following table describes which terminal configurations are supported by the PFI channels on the device.
| PFI Channel | Location | Terminal Configuration |
|---|---|---|
| 0 | NI 656x front panel | TTL/CMOS only |
| 1, 2 | DDC connector | LVDS only |
| 3 | DDC connector | LVDS or TTL/CMOS, software-selectable |
Triggers and events must be individually configured to use LVDS or single-ended terminal configurations using NI-HSDIO.
When the Sample clock is exported to the DDC connector, both an LVDS and an LVPECL version of the clock signal are exported.
You do not need to configure voltage levels to use the NI 656x. Using the NI-HSDIO Configure Voltage functions or VIs with the NI 656x returns an error.
For more information about voltage level ranges and resolutions, refer to NI 656x specifications.