Source Impedance

The NI 654x data, clock, and event generation channels have a 50 Ω source impedance. For applications where the full voltage swing is required at the DUT, a parallel termination resistance of 1 kΩ to 10 kΩ is recommended. With a system terminated by 10 kΩ, much of the signal reflections are eliminated by the source 50 Ω termination and the parallel termination. Thus the voltage seen at the termination resistor is 99.5% of the configured voltage.

Because the NI 654x interface cable (NI SHC68-C68-D2) is a 50 Ω transmission line, when you use 3.3 V Logic, you can build matched impedance systems with a 50 Ω parallel termination as the load. While a matched system is beneficial because all reflections are eliminated, the voltage at the termination is one-half of the generation voltage level. The change in voltage is caused by the voltage divider that is created by the source and termination impedance, as shown in the following figure.

Use the following formula to calculate the voltage sensed at the termination point, V_TERM.

where    V_O is the voltage driven by the NI 654x,

R_Term is the termination impedance,

R_Source is the source impedance

For example, if R_SOURCE = 50 Ω and if the termination resistance is also set to 50 Ω, then the voltage level seen at the termination is one-half the source voltage.

Always calculate the maximum current that the NI 654x in your test system can source and sink. You can calculate the maximum current using the following formula:

Max current = V_{OH (max)}/(50 + R_Term)

For example, if the device is driving 1.8 V into a 50 Ω load, the maximum current would be calculated as follows:

I_max = 1.8 V/(50 Ω + 50 Ω) = 18 mA

18 mA is higher than the NI 654x current specification at 1.8 V Logic operation; therefore, the device should not be connected to a 50 Ω load when using the 1.8 V Logic family.

Note

Refer to the NI 654x specifications for details on the maximum current that the NI 654x can source for each generation voltage setting.

The NI 654x generation lines can be programmatically set to a high-impedance (tristate) state when not in use. Upon power up, DDC CLK OUT, CLK OUT, DIO<0..31>, and PFI <0..3> are set to tristate and remain in that state until configured for generation.

Refer to Termination and Terminating Your Module for more information about signal reflections and termination.