Triggers:Pause:Digital Level:Position
Short Name: PauseTrig.DigLevel.Position
Specifies the position where the start trigger is latched, relative to the Sample clock. Trigger voltages and positions are only relevant if the trigger source is a front panel connector.
| Sample clock rising edge (18) | The Pause trigger asserts on the Sample clock rising edge. |
| Sample clock rising edge (19) | The Pause trigger asserts on the Sample clock falling edge. |
| Delay from Sample clock rising edge (20) | The Pause trigger asserts after a delay from the Sample clock rising edge. Specify the delay using the Data Position Delay property. This choice has more jitter than the rising or falling edge values. Certain devices have Sample clock frequency limitations on when a custom delay can be used. Refer to the device documentation for details. |
Remarks
The following table lists the characteristics of this property.
| Data Type | ViInt32 |
| Permissions | R/W |
| Channel Based | No |
| High-Level VI | None |