Data Position Settings

You have three available data position settings for acquisition and generation channels:

• Sample clock rising edge—Data is generated/acquired on the rising edge of the clock driving the operation.
• Sample clock falling edge—Data is generated/acquired on the falling edge of the clock driving the operation.
• Delay from Sample clock rising edge—Data is generated/acquired at a specified time (specified in the niHSDIO Configure Data Position Delay VI or the niHSDIO_ConfigureDataPositionDelay function) after the rising edge of the clock driving the operation. The data position delay resolution depends on your clock frequency.

Note  NI 656x devices have special considerations for legal delayed data settings for Sample clock frequencies between 25 and 50 MHz.

Refer to the Acquisition and Generation books for your device for timing diagrams illustrating changing data position.

Refer to Configuring Data Position for more information about using NI-HSDIO to configure data position.