Clock Sources Summary
The following tables describe the clock sources available for the NI 656x. These clock sources are shown in the Clocking diagram. For a more general description of these clocks, refer to Clocks for Digital Waveform Generator/Analyzers.
Sample Clock | |||
| Clock Source | Used In | Location | Description |
|---|---|---|---|
| On Board Clock | Acquisition, Generation | Internal | The NI 656x provides a single high-precision 200 MHz voltage-controlled crystal oscillator (VCXO) clock source. The NI 656x can generate any clock frequency of 200 MHz/n, where n is any integer from 1 to 4,194,304 for the NI 6562, and 2 to 4,194,304 for the NI 6561. For example, for the NI 6562, the On Board Clock can run at 200 MHz, 100 MHz, 66.67 MHz, 50 MHz, 40 MHz, 33.33 MHz, 28.57 MHz, 25 MHz, 22.22 MHz, and so on. The onboard PLL allows the On Board Clock to be phase-locked to the Reference clock, if one is provided. |
| CLK IN | Acquisition, Generation | Front panel SMB jack connector | The CLK IN SMB jack is intended for use as an external frequency input channel, allowing you to provide an alternate frequency as the Sample clock rate. The CLK IN signal can be any sine or square wave signal that meets the specifications provided in the NI 656x specifications. The CLK IN signal must be free running. |
| PXI_STAR (NI PXI-6561/6562 only) |
Acquisition, Generation | Backplane | The PXI_STAR connector can be used as an external frequency input channel, allowing you to provide an alternate frequency as the Sample clock rate. The PXI_STAR signal specifications are provided in the NI 656x specifications. The PXI_STAR signal must be free running. |
Reference Clock | |||
| Clock Source | Used In | Location | Description |
| NONE | Acquisition, Generation | Internal | When no reference clock source is selected, the PLL is not locked and the On Board Clock has no known phase relationship to any other clocks in the system. |
| CLK IN | Acquisition, Generation | Front panel SMB jack connector | The CLK IN SMB jack can be used to provide an external Reference clock for the PLL. The CLK IN signal can be any sine or square wave signal that meets the specifications provided in the NI 656x specifications. The CLK IN signal must be free running. |
| PXI_CLK10 | Acquisition, Generation | PXI trigger bus | The PXI Clock 10 line exists on the PXI backplane and provides a 10 MHz reference clock to all slots in the chassis. The PLL can be configured to lock to this signal. |
| RTSI 7 (NI PCI-6561/6562 only) | Acquisition, Generation | RTSI trigger bus | The Onboard Reference Clock can be routed to RTSI 7 to provide a 10 MHz reference clock signal to the NI 654x and other devices that share the RTSI bus. The PLL can be configured to lock to this signal. |
STROBE |
|||
| Clock Source | Used In | Location | Description |
| STROBE | Acquisition | DDC connector | STROBE is intended for use as the Sample clock for dynamic acquisition sessions when source-synchronous transfers are desired (that is, when the data and clock travel together through the cable from the DUT to the NI 656x). The STROBE signal must be a free-running LVDS signal. |