Clock Position Settings
You have three available clock position settings for the position of the exported Sample clock:
- Inverted—The exported Sample clock is an inverted copy of the Sample clock.
- Noninverted—The exported Sample clock is an exact copy of the Sample clock.
- Delayed—The exported Sample clock is a delayed version of the Sample clock, delayed by 0 to 1 of the Sample clock periods. The data position delay resolution depends on your clock frequency.
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Notes Because the data position is relative to the Sample clock, changes to the exported Sample clock position do not affect the timing of the data channel operations. |
| NI 656x devices have special considerations for exporting the Sample clock at frequencies between 25 and 50 MHz. |
Related Topics:
- Dynamic Generation Timing Diagrams (NI 654x)
- Dynamic Generation Timing Diagrams (NI 655x)
- Dynamic Generation Timing Diagrams (NI 656x)
- Advanced Attributes