Front Panel and Connector Pinout
From NI Digital Waveform Generator/Analyzer
Front Panel and Connector Pinout
The NI 656x front panel, shown below, has three SMB jack connectors and one 73-pin Digital Data & Control (DDC) 12x Infiniband connector. The SMB jack connectors are described in the SMB Jack Connector Names and Descriptions table. The DDC connector signals are described in the DDC Connector Names and Descriptions table.
| Note If you design a custom cabling solution with connector (779157-01) and cable (192744-01), the NI 656x pinout is reversed at the end connector. For example, the signal shown on pin 1 shown in the previous figure would map to pin 73 at the end connector. |
SMB Jack Connector Names and Descriptions
| Connector | Signal Name | Signal Type | Signal Description | ||
|---|---|---|---|---|---|
| CLK IN | Reference/Clock Input | Control | External reference clock used for the PLL or for the external Sample clock used for pattern generation and/or acquisition. | ||
| PFI 0 | Programmable Function Interface (PFI) 0 | Control | Input terminal to the NI 656x for external triggers or the output terminal from the NI 656x for events. | ||
| CLK OUT | Reference/Clock Output | Control | Terminal for the exported PLL Reference clock or the exported Sample clock. | ||
DDC Connector Names and Descriptions |
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| Pins | Signal Name | Signal Type | Signal Description | ||
| 65 | DDC CLK OUT LVDS | Control | Positive terminal for the LVDS exported Sample clock. | ||
| 66 | DDC CLK OUT LVDS* | Control | Complementary terminal for the LVDS exported Sample clock. | ||
| 71 | DDC CLK OUT LVPECL | Control | Positive terminal for the LVPECL exported Sample clock. | ||
| 72 | DDC CLK OUT LVPECL* | Control | Complementary terminal for the LVPECL exported Sample clock. | ||
| 62 | STROBE | Control | Positive external Sample clock source that can be used for dynamic acquisition. | ||
| 63 | STROBE* | Control | Complementary external Sample clock source that can be used for dynamic acquisition. | ||
| 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 59 | DIO <0..15> | Data | Positive bidirectional digital I/O data channels 0 through 15. | ||
| 15, 18, 21, 24, 27, 30, 33, 36, 39, 42, 45, 48, 51, 54, 57, 60 | DIO <0..15>* | Data | Complementary bidirectional digital I/O data channels 0 through 15. | ||
| 2, 5, 8 | PFI<1..3> | Control | Positive input terminals to the NI 656x for external triggers or output terminals from the NI 656x for events. | ||
| 3, 6, 9 | PFI<1..3>* | Control | Complementary input terminals to the NI 656x for
external triggers or output terminals for the NI 656x for
events.
|
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| 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 43, 46, 49, 52, 55, 58 | GND | Ground | Ground reference for signals. | ||
| 11, 12, 68, 69 | RESERVED | N/A | These terminals are reserved for future use. Do not connect to these pins. | ||