Glossary

NI Digital Waveform Generator/Analyzer

Glossary

Prefix	Meaning	Value
p	pico	10^-12
n	nano	10^-9
µ	micro	10^-6
m	milli	10^-3
k	kilo	10³
M	mega	10⁶
G	giga	10⁹

Numbers and Symbols

°	degrees
-	negative of, or minus
<	less than
>	greater than
≤	less than or equal to
≥	greater than or equal to
Ω	ohms
/	per
%	percent
±	plus or minus
A
A	amps
aberration	Signal distortions that cause imperfections in the shape or sharpness of the signal.
active drive	A drive type where the generation voltage high level is configured as the voltage produced at the channel electronics when the Pattern Generation Engine generates a binary one.
ADE	application development environment
API	application programming interface—a standardized set of subroutines or functions, along with the parameters that a program can call.
asynchronous	For hardware, it is a property of an event that occurs at an arbitrary time, without synchronization to a reference clock. In software, it is the property of a function that begins an operation and returns prior to the completion or termination of the operation.
B
b	bits
B	bytes
bidirectional data channels	Data channels that can be programmatically configured as acquisition or generation.
bit	Single value for a single position in time, on a single line. A bit can have four possible values: 0, 1, X, and Z.
buffer	Temporary storage for acquired or generated data (software). A collection of samples.
bus	Group of conductors that interconnect individual circuitry in a computer. Typically, a bus is the expansion vehicle to which I/O or other devices are connected. A logical grouping of multiple channels.
C
cache	High-speed processor memory that buffers commonly used instructions or data to increase processing throughput.
channel	Single digital terminal, used for generating and/or acquiring data.
characteristic impedance	Transmission line parameter that determines how propagating signals are transmitted or reflected in the line.
clock	Hardware component that controls timing for reading from or writing to channels. Periodic digital edges that can be used to measure time.
CompactPCI	Core specification defined by the PCI Industrial Computer Manufacturer's Group (PICMG).
compare data	Expected response data from your device under test (DUT).
control signals	Signals that regulate/control the data transfer.
counter/timer	A circuit that counts external pulses or clock pulses (timing).
crosstalk	Ratio, in dB, of the level of the interference on the affected channel to the actual level of the interfering signal.
current sinking	The ability to dissipate current for analog or digital signals.
current sourcing	The ability to supply current for analog or digital signals.
D
DAQ	Data Acquisition—Collecting and measuring electrical signals from sensors, transducers, and test probes or fixtures and inputting them to a computer for processing. Also refers to collecting and measuring the same kinds of electrical signals with analog-to-digital and/or digital devices plugged into a PC, and possibly generating control signals with digital-to-analog and/or digital devices in the same PC.
Data Active event	The Data Active event indicates when the Pattern Generation Engine is generating data. If the Pattern Generation Engine is waiting for a trigger or is paused, the Data Active event is deasserted. When the Pattern Generation Engine is generating data, the Data Active event is asserted, synchronous with the data.
data interpretation	Data interpretation determines whether the input signal is acquired as a 0 or a 1, based on how it relates to the Acquisition Voltage High and Low Levels and the configured data interpretation mode. In High or Low mode, when the input signal is sampled below Acquisition Voltage Low Level, a 0 is received. A 1 is not recognized until the acquired signal passes above Acquisition Voltage Low Level and above Acquisition Voltage High Level. Conversely, if the acquired signal was last sampled above Acquisition Voltage High (as a 1), the signal is not be sampled as a 0 until the signal is sampled below Acquisition Voltage High Level and below Acquisition Voltage Low Level. In Valid or Invalid mode, signals sampled between the Acquisition Voltage High and Acquisition Voltage Low Levels are returned as a 1, while signals sampled either above Acquisition Voltage High Level or below Acquisition Voltage Low Level are returned as a 0.
data rate multiplier	an attribute that specifies whether the device to acquires or generates in single data rate (SDR) mode or in double data rate (DDR) mode.
DC	direct current
default setting	Default parameter value recorded in the driver. In many cases, the default input of a control is a certain value (often 0) that means use the current default setting.
device	Plug-in data acquisition board, card, or pad that can contain multiple channels and conversion devices. Plug-in boards, PCMCIA cards, and devices that connects to your computer parallel port, are all examples of DAQ devices.
differential circuitry	Circuitry that actively responds to the difference between two terminals, rather than the difference between one terminal and ground.
digital trigger	Level signal having two discrete levels: a high and a low level. See trigger.
DIO	digital input/output
Direct DMA	Direct DMA can be used to transfer waveform data to the onboard memory at rates well beyond the typical 5 to 30 MB/sec range in a standard PC-based architecture by establishing a direct connection between the onboard memory and a specialized waveform data source.
drift	Clock drift occurs when the transmitter's clock period is slightly different from that of the receiver. After many clock cycles, the difference between the two periods becomes noticeable and may cause loss of synchronization and other errors.
drive data	Provided stimulus data to your device under test (DUT) from your NI digital waveform generator/analyzer.
drive type	Describes the behavior of the generation channels, and what the generation channels do when set to high level.
DUT	device under test
E
End of Record event	An event that indicates when the device enters its Record Complete state, which indicates that the current record has been acquired.
event	Events are emitted to signify a device state change, the arrival of a certain kind of sample, the production of a certain number of samples, or the passage of time.
eye diagram	Diagram constructed by looking at the outputs of a digital transmitter over three periods of the main system clock. For more information, refer to the Digital Waveform Timing document on ni.com/zone.
F
fall time	The time that it takes a signal to fall from 80% to 20% of the voltage between the voltage low level and the voltage high level.
fetch	An operation that transfers acquired waveform data from device memory to PC memory.
FPGA	field-programmable gate array—Fundamentally, an FPGA is a semi-conductor device which contains a large quantity of gates (logic devices), which are not interconnected, and whose function is determined by a wiring list, which is downloaded to the FPGA.
function	Set of software instructions executed by a single line of code that can have input and/or output parameters and returns a value when executed.
G
group	Collection of lines.
H
high level	For generation, the high level is the voltage produced when a binary one is generated. For acquisition, the high level is the voltage threshold above which the input will be sampled as a binary one.
I
I/O	input/output—Transfer of data to/from a computer system involving communications channels, operator interface devices, and/or data acquisition and control interfaces.
idle state	Specifies the values of the channels when the generation operation is paused or has completed.
I_IH	current input high—The maximum amount of current required on the input pin when the voltage on the input pin is higher than V_IH.
I_IL	current input low—The maximum amount of current required on the input pin when the voltage on the input pin is lower than V_IL.
Initial state	Specifies the values of the channels when the generation operation has not yet started.
instructions	Statements used to define a script.
interrupt	Computer signal indicating that the CPU should suspend its current task to service a designated activity.
inter-symbol interference	In a digital transmission system, distortion of the received signal, in which distortion in the form of temporal spreading and consequent overlap of individual pulses to the degree that the receiver cannot reliably distinguish between state changes.
I_OH	current output high—The minimum amount of available current on the output pin when the logic device is driving a logic high.
I_OL	current output low—The minimum amount of available current on the output pin when the logic device is driving a logic low.
J
jitter	The deviation from ideal timing of an event. Jitter is typically measured from the zero-crossing of a reference signal. Jitter typically comes from crosstalk, simultaneous switching outputs, and other regularly occurring interference signals.
L
line	Represents the value of one bit of a sample over all samples. A line is independent of any hardware I/O connector.
line group	A collection of lines displayed as a single plot on a digital waveform graph.
line name	Name of a line within a sample or buffer.
low level	For generation, the low level is the voltage produced when a binary zero is generated. For acquisition, the low level is the voltage threshold below which the input will be sampled as a binary one.
LSB	least significant bit
LVDM	LVDM is an LVDS-compatible standard that allows for a 100 O parallel termination at the source.
LVDS	low voltage differential signaling. A low-noise, low-power, low-amplitude method for high-speed digital data transfer.
M
Marker event	The Marker event is a general-purpose event that is configured within a generation script. The Marker event can be asserted synchronous to any even numbered sample within a waveform within a script.
MB/s	Unit for data transfer that means one million or 10⁶ bytes per second.
Measurement & Automation Explorer (MAX)	Controlled, centralized configuration environment that allows you to configure all of your National Instruments DAQ, GPIB, HSDIO, IMAQ, IVI, Motion, and VISA devices.
MSB	most significant bit
N
NIM	noise immunity margin—Extra margin between the voltage level being driven by the source and the voltage level required at the destination.
O
On Board Clock	For NI Digital Waveform Generator/Analyzers, this term refers to the onboard voltage-controlled crystal oscillator (VCXO) clock source.
Onboard Reference clock	On PCI devices, the Onboard Reference Clock is the 10 MHz signal you can export to RTSI 7 on the RTSI trigger bus.
open collector	A drive type where the generation voltage high level is configured as the high-impedance state.
overshoot	Overshoot is a peak distortion following an edge.
P
parallel termination	Termination that matches the characteristic impedance of the medium at the end of the transmission line.
Pause trigger	Trigger used to indicate to the device that it should stop generating and/or acquiring. The device resumes when the pause trigger becomes inactive.
PFI	Programmable Function Interface. I/O channels to the digital waveform generator/analyzer. Functionality and specifications will vary by device and operation.
pin number	See terminal.
posttrigger	Acquiring data that occurs after a trigger.
preshoot	Preshoot is a peak distortion preceding an edge.
pretrigger	Acquiring data that occurs before a trigger.
programmable function interface	See PFI.
propagation delay	The amount of time required for a signal to pass through a circuit.
protocol	The exact sequence of bits, characters and control codes used to transfer data between computers and peripherals through a communications channel, such as the GPIB.
PXI	PCI eXtensions for Instrumentation—Rugged, open system for modular instrumentation based on CompactPCI, with special mechanical, electrical, and software features.
PXI trigger bus	PXI equivalent of the RTSI bus, with additional timing and synchronization capabilities.
R
Ready for Advance event	An event that indicates when the device enters its Wait for Advance Trigger state, which indicates that the acquisition of the previous record is complete.
Ready for Start event	For both acquisition and generation, the Ready For Start event indicates that the NI digital waveform/generator analyzer is configured and ready to receive a Start trigger.
real time	Property of an event or system in which data is processed as it is acquired instead of being accumulated and processed at a later time.
Reference clock	Clock to which a device phase locks another, usually faster, clock. A common source for the reference clock is the 10 MHz oscillator present on the PXI backplane.
Reference trigger	This trigger establishes the reference point that separates pretrigger and posttrigger samples.
rise time	The time that it takes a signal to rise from 20% to 80% of the voltage between the voltage low level and the voltage high level.
round trip delay	Time required for the data to move from the digital tester, through the cable and DUT, and back to the tester.
R_source	source impedance
RTD	See round trip delay.
R_term	termination impedance
RTSI bus	Real-Time System Integration Bus—The National Instruments timing bus that connects DAQ devices directly, by means of connectors on top of the devices, for precise synchronization of functions.
S
s	seconds
S	sample
sample	The value being generated/acquired on all of the digital data channels during a single sample clock cycle.
Sample clock	Samples are generated or acquired based on Sample clock cycles.
Sample Error event	An event that indicates when the device detects a sample where the actual response and the expected response do not match.
script	Collection of instructions that describe the order and timing of one or more waveforms.
Script trigger	General-purpose trigger that has a role that is determined by the context of the script.
series termination	Termination that places series impedance equal to the characteristic impedance at the source of the transmission line.
settling time	Time required for an amplifier, relay, or other circuits to reach a stable mode of operation.
signal	Means of conveying information. In this help file, signal refers to a digital transmission.
software trigger	Programmed event that triggers an operation such as data acquisition.
Start trigger	The Start trigger transitions a device into a state where the device can respond to Sample clocks. For an acquisition session, the device starts sampling and storing data. For a generation session, the device starts generating samples.
static acquisition	Software-timed (nonclocked) that returns the current digital logic state of the configured data channels with each read.
static generation	Software-timed (nonclocked) that sets the current state of the configured data channels to the requested digital logic state.
streaming	A method of generating waveforms that are too large to fit in device onboard memory by filling an allocated portion of onboard memory with the first part of the waveform; and as the waveform is generated and space becomes free in onboard memory, refilling the space with new waveform data.
strobed I/O	Any operation where every data transfer is timed by hardware signals. For software, it is a property of a function that begins an operation and returns only when the operation is complete.
synchronous	For hardware, it is a property of an event that occurs at a particular time, synchronized to a clock.
T
terminal	Named location where a signal is either produced (generated) or consumed (acquired).
t_fall	fall time
t_pd	propagation delay
transfer rate	Rate, measured in bytes/s or samples/s, at which data is moved from source to destination after software initialization and set up operations; the maximum rate at which the hardware can operate.
trigger	A signal sent to the device to control the device in some way. In the context of the NI digital waveform generator/analyzer, triggers are essentially the opposite of events.
t_rise	rise time
t_s	settling time
TTL	transistor-transistor logic
U
unstrobed I/O	Basic digital I/O operations that do not involve the use of control signals in data transfers. Unstrobed data transfers are controlled by software commands. Also known as software-timed I/O.
V
V	volts
VCXO	voltage-controlled crystal oscillator
vector	See sample.
VHDCI	very high-density connector interface
VI	Virtual Instrument A combination of hardware and/or software elements, typically used with a PC, that has the functionality of a classic stand-alone instrument. A LabVIEW software module (VI), which consists of a front panel user interface and a block diagram program.
V_IH	voltage input high—The input voltage level at or above which the logic device senses a binary one.
V_IL	Input voltage level at or below which the logic device senses a binary zero.
virtual channels	Channel names that can be defined outside the application and used without having to perform scaling operations.
V_OD	differential output voltage—The difference in voltage between the positive and complementary conductors of a differential transmission. Can be thought of as the difference of the two conductors.
V_OH	voltage output high—The generated voltage level at the output pin when the logic device outputs a binary one.
V_OL	voltage output low—The generated voltage level at the output pin when the logic device outputs a binary zero.
V_OS	offset voltage—The common mode of the differential signal. Can be thought of as the average of the two conductors.
V_RANGE	input voltage range—The absolute voltage, referenced to common, allowed by the receiver.
V_TH	threshold voltage—the differential voltage threshold at which the receiver registers a valid logic state.
W
waveform	A collection of digital samples generated or acquired at the DDC connector.
X
x	Bit state meaning that the channel is ignored.
Z
z	Bit state meaning that the channel is set to high-impedance.
Z₀	The characteristic AC impedance of the transmission line.
Z_s	The impedance at the source of the transmission line.
Z_t	The impedance at the destination of the transmission line.

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