Alphabetical Attribute List and Default Values

NI Digital Waveform Generator/Analyzer

Alphabetical Attribute List and Default Values

The following table lists the default values for each property you can configure for your device. An "N/A" in a table cell indicates that the listed property is not supported for that device. A dash indicates that the property does not have a default value or that it is a read-only property. "" is used in the following ways:

In output terminal properties to indicate to the device not to export the relevant signal
In trigger source properties to the device that the relevant trigger is not used
In dynamic and static channels to means "all channels"

C/C++ Attribute	NI 654x Default Value	NI 655x Default Value	NI 656x Default Value
ADVANCE TRIGGER TYPE	NONE	NONE	NONE
DATA_ACTIVE_EVENT _LEVEL_ACTIVE_LEVEL	ACTIVE_HIGH	ACTIVE_HIGH	ACTIVE_HIGH
DATA_ACTIVE_EVENT _OUTPUT_TERMINAL	""	""	""
DATA_ACTIVE_EVENT_POSITION	SAMPLE_CLOCK _RISING_EDGE	SAMPLE_CLOCK _RISING_EDGE	SAMPLE_CLOCK _RISING_EDGE
DATA_ACTIVE_EVENT _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
DATA_ACTIVE_INTERNAL_ROUTE_DELAY	N/A	0	N/A
DATA_INTERPRETATION	HIGH_OR_LOW	HIGH_OR_LOW	HIGH_OR_LOW
DATA_POSITION	SAMPLE_CLOCK _RISING_EDGE	SAMPLE_CLOCK _RISING_EDGE	SAMPLE_CLOCK _RISING_EDGE
DATA_POSITION_DELAY	0 %	0 %	0 %
NIHSDIO_ATTR_DATA_RATE_MULTIPLIER	SINGLE_DATA_RATE	SINGLE_DATA_RATE	SINGLE_DATA_RATE
NIHSDIO_ATTR_DATA_TRANSFER_BLOCK_SIZE	0	0	0
DATA_VOLTAGE_HIGH_LEVEL	3.3 V logic family voltage levels. Refer to device specifications for more information.	3.3 V logic family voltage levels. Refer to device specifications for more information.	N/A
DATA_VOLTAGE_LOW_LEVEL	3.3 V logic family voltage levels. Refer to device specifications for more information.	3.3 V logic family voltage levels. Refer to device specifications for more information.	N/A
NIHSDIO_ATTR_DATA_WIDTH	4	4	2
DIGITAL_EDGE_ADVANCE _TRIGGER_EDGE	RISING_EDGE	RISING_EDGE	RISING_EDGE
DIGITAL_EDGE_ADVANCE _TRIGGER_IMPEDANCE	10000 Ω	10000 Ω	10000 Ω
DIGITAL_EDGE_ADVANCE _TRIGGER_POSITION	SAMPLE_CLOCK _RISING_EDGE	SAMPLE_CLOCK _RISING_EDGE	SAMPLE_CLOCK _RISING_EDGE
DIGITAL_EDGE_ADVANCE _TRIGGER_SOURCE	""	""	""
DIGITAL_EDGE_ADVANCE_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
DIGITAL_EDGE_REF _TRIGGER_EDGE	RISING_EDGE	RISING_EDGE	RISING_EDGE
DIGITAL_EDGE_REF _TRIGGER_IMPEDANCE	10000 Ω	10000 Ω	10000 Ω
DIGITAL_EDGE_REF _TRIGGER_POSITION	SAMPLE_CLOCK_RISING_EDGE	SAMPLE_CLOCK_RISING_EDGE	SAMPLE_CLOCK_RISING_EDGE
DIGITAL_EDGE_REF_TRIGGER_SOURCE	""	""	""
DIGITAL_EDGE_REF_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
DIGITAL_EDGE_SCRIPT_TRIGGER_EDGE	RISING_EDGE	RISING_EDGE	RISING_EDGE
DIGITAL_EDGE_SCRIPT _TRIGGER_IMPEDANCE	10000 Ω	10000 Ω	10000 Ω
DIGITAL_EDGE_SCRIPT _TRIGGER_SOURCE	""	""	""
DIGITAL_EDGE_SCRIPT_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
DIGITAL_EDGE_START _TRIGGER_EDGE	RISING_EDGE	RISING_EDGE	RISING_EDGE
DIGITAL_EDGE_START _TRIGGER_IMPEDANCE	10000 Ω	10000 Ω	10000 Ω
DIGITAL_EDGE_START _TRIGGER_POSITION	SAMPLE_CLOCK_RISING_EDGE	SAMPLE_CLOCK_RISING_EDGE	SAMPLE_CLOCK_RISING_EDGE
START_TRIGGER_SOURCE	""	""	""
DIGITAL_EDGE_START_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
DIGITAL_LEVEL_PAUSE _TRIGGER_IMPEDANCE	10000 Ω	10000 Ω	10000 Ω
DIGITAL_LEVEL_PAUSE _TRIGGER_POSITION	SAMPLE_CLOCK_RISING_EDGE	SAMPLE_CLOCK_RISING_EDGE	SAMPLE_CLOCK_RISING_EDGE
DIGITAL_LEVEL_PAUSE _TRIGGER_SOURCE	""	""	""
DIGITAL_LEVEL_PAUSE_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
DIGITAL_LEVEL_PAUSE _TRIGGER_WHEN	HIGH	HIGH	HIGH
DIGITAL_LEVEL_SCRIPT _TRIGGER_IMPEDANCE	10000 Ω	10000 Ω	10000 Ω
DIGITAL_LEVEL_SCRIPT _TRIGGER_SOURCE	""	""	""
DIGITAL_LEVEL_SCRIPT_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
DIGITAL_LEVEL_SCRIPT _TRIGGER_WHEN	HIGH	HIGH	HIGH
DIRECT_DMA_ENABLED	VI_FALSE	VI_FALSE	VI_FALSE
DIRECT_DMA_WINDOW_ADDRESS	0	0	0
DIRECT_DMA_WINDOW_SIZE	0	0	0
DYNAMIC_CHANNELS	""	""	""
END_OF_RECORD_EVENT _OUTPUT_TERMINAL	""	""	""
END_OF_RECORD_EVENT _PULSE_POLARITY	ACTIVE_HIGH	ACTIVE_HIGH	ACTIVE_HIGH
END_OF_RECORD_EVENT _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
EVENT_VOLTAGE_HIGH_LEVEL	3.3 V logic family voltage levels. Refer to device specifications for more information.	3.3 V logic family voltage levels. Refer to device specifications for more information.	N/A
EVENT_VOLTAGE_LOW_LEVEL	3.3 V logic family voltage levels. Refer to device specifications for more information.	3.3 V logic family voltage levels. Refer to device specifications for more information.	N/A
EXPORTED_ADVANCE_TRIGGER _OUTPUT_TERMINAL	""	""	""
EXPORTED_ADVANCE_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
EXPORTED_ONBOARD_REF_CLOCK _OUTPUT_TERMINAL	""	""	""
EXPORTED_PAUSE_TRIGGER _OUTPUT_TERMINAL	""	""	""
EXPORTED_PAUSE_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
EXPORTED_REF_CLOCK _OUTPUT_TERMINAL	""	""	""
EXPORTED_REF_TRIGGER _OUTPUT_TERMINAL	""	""	""
EXPORTED_REF_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
EXPORTED_SAMPLE_CLOCK_DELAY	0 %	0 %	0 %
EXPORTED_SAMPLE_CLOCK_MODE	NONINVERTED	NONINVERTED	NONINVERTED
EXPORTED_SAMPLE_CLOCK_OFFSET	2.5 ns	2.5 ns	1.5 ns
EXPORTED_SAMPLE_CLOCK _OUTPUT_TERMINAL	""	""	""
EXPORTED_SCRIPT_TRIGGER _OUTPUT_TERMINAL	""	""	""
EXPORTED_SCRIPT_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
EXPORTED_START_TRIGGER _OUTPUT_TERMINAL	""	""	""
EXPORTED_START_TRIGGER _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
FETCH_BACKLOG	—	—	—
FETCH_OFFSET	0 S	0 S	0 S
FETCH_RELATIVE_TO	MOST_RECENT_SAMPLE when Reference trigger is not configured; REFERENCE_TRIGGER when Reference trigger is configured	MOST_RECENT_SAMPLE when Reference trigger is not configured; REFERENCE_TRIGGER when Reference trigger is configured	MOST_RECENT_SAMPLE when Reference trigger is not configured; REFERENCE_TRIGGER when Reference trigger is configured
NIHSDIO_ATTR_HWC_FILTER_REPEATED_SAMPLE_ERRORS	N/A	VI_FALSE	N/A
GENERATION_MODE	WAVEFORM	WAVEFORM	WAVEFORM
NIHSDIO_ATTR_HWC_HARDWARE_COMPARE_MODE	Disabled	Disabled	Disabled
IDLE_STATE	HOLD_LAST_VALUE	HOLD_LAST_VALUE	HOLD_LAST_VALUE
INITIAL_STATE	HOLD_LAST_VALUE	HOLD_LAST_VALUE	HOLD_LAST_VALUE
INPUT_IMPEDANCE	50 Ω	50 Ω	50 Ω
MARKER_EVENT _OUTPUT_TERMINAL	""	""	""
MARKER_EVENT_POSITION	SAMPLE_CLOCK _RISING_EDGE	SAMPLE_CLOCK _RISING_EDGE	SAMPLE_CLOCK _RISING_EDGE
MARKER_EVENT_PULSE_POLARITY	ACTIVE_HIGH	ACTIVE_HIGH	ACTIVE_HIGH
MARKER_EVENT _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
NUM_RECORDS	1	1	1
NIHSDIO_ATTR_HWC_NUM_SAMPLE_ERRORS	—	—	—
OSCILLATOR_PHASE_DAC_VALUE	0	0	0
PATTERN_MATCH_ADVANCE _TRIGGER_PATTERN	""	""	""
PATTERN_MATCH_ADVANCE _TRIGGER_WHEN	PATTERN_MATCHES	PATTERN_MATCHES	PATTERN_MATCHES
PATTERN_MATCH_PAUSE _TRIGGER_PATTERN	""	""	""
PATTERN_MATCH_PAUSE _TRIGGER_WHEN	PATTERN_MATCHES	PATTERN_MATCHES	PATTERN_MATCHES
PATTERN_MATCHES_REF _TRIGGER_PATTERN	""	""	""
PATTERN_MATCH_REF _TRIGGER_WHEN	PATTERN_MATCHES	PATTERN_MATCHES	PATTERN_MATCHES
PATTERN_MATCH_START _TRIGGER_PATTERN	""	""	""
PATTERN_MATCH_START _TRIGGER_WHEN	PATTERN_MATCHES	PATTERN_MATCHES	PATTERN_MATCHES
PAUSE_TRIGGER_TYPE	NONE	NONE	NONE
READY_FOR_ADVANCE_EVENT _LEVEL_ACTIVE_LEVEL	ACTIVE_HIGH	ACTIVE_HIGH	ACTIVE_HIGH
READY_FOR_ADVANCE_EVENT _OUTPUT_TERMINAL	""	""	""
READY_FOR_ADVANCE_EVENT _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
READY_FOR_START_EVENT _LEVEL_ACTIVE_LEVEL	ACTIVE_HIGH	ACTIVE_HIGH	ACTIVE_HIGH
READY_FOR_START_EVENT _OUTPUT_TERMINAL	""	""	""
READY_FOR_START_EVENT _TERMINAL_CONFIGURATION	SINGLE_ENDED	SINGLE_ENDED	LVDS
RECORDS_DONE	—	—	—
REF_CLOCK_IMPEDANCE	50 Ω	50 Ω	100 Ω
REF_CLOCK_RATE	10M	10M	10M
REF_CLOCK_SOURCE	""	""	""
REF_TRIGGER_PRETRIGGER_SAMPLES	0	0	0
REF_TRIGGER_TYPE	NONE	NONE	NONE
REPEAT_COUNT	1	1	1
REPEAT_MODE	FINITE	FINITE	FINITE
SAMPLE_CLOCK_IMPEDANCE	50 Ω	50 Ω	100 Ω
SAMPLE_CLOCK_RATE	50 MHz	50 MHz	50 MHz
SAMPLE_CLOCK_SOURCE	ON_BOARD _CLOCK_STR	ON_BOARD _CLOCK_STR	ON_BOARD _CLOCK_STR
NIHSDIO_ATTR_HWC_SAMPLE_ERROR_BACKLOG	N/A	—	N/A
NIHSDIO_ATTR_HWC_SAMPLE_ERROR_BUFFER_OVERFLOWED	N/A	—	N/A
NIHSDIO_ATTR_HWC_SAMPLES_COMPARED	N/A	—	N/A
SAMPLES_PER_RECORD	1000	1000	1000
SCRIPT_TO_GENERATE	""	""	""
SCRIPT_TRIGGER_TYPE	NONE	NONE	NONE
NIHSDIO_ATTR_SERIAL_NUMBER	—	—	—
SPACE_AVAILABLE_IN_STREAMING_WAVEFORM	0	0	0
START_TRIGGER_TYPE	NONE	NONE	NONE
STATIC_CHANNELS	""	""	""
STREAMING_ENABLED	VI_FALSE	VI_FALSE	VI_FALSE
STREAMING_WAVEFORM_NAME	""	""	""
TOTAL_ACQUISITION_SIZE	—	—	—
TOTAL_GENERATION_SIZE	—	—	—
TRIGGER_VOLTAGE_HIGH_LEVEL	3.3 V logic family voltage levels. Refer to device specifications for more information.	3.3 V logic family voltage levels. Refer to device specifications for more information.	N/A
TRIGGER_VOLTAGE_LOW_LEVEL	3.3 V logic family voltage levels. Refer to device specifications for more information.	3.3 V logic family voltage levels. Refer to device specifications for more information.	N/A
WAVEFORM_TO_GENERATE	""	""	""

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