Channel Electronics

The channel electronics of NI 656x devices consist of LVDM buffers and the appropriate termination resistors. LVDM is an LVDS-compatible standard that allows for a 100 Ω parallel termination at the source and destination, which provides for the software-selectable direction control feature of the NI 656x. Each I/O channel is capable of simultaneously driving and receiving data.

The following figure provides a basic block diagram for the channel electronics. Refer to NI 656x Block Diagram for a picture of how the channel electronics circuitry fits into the overall block diagram.

Dynamic Generation

For dynamic generation operations, the data signal appears at the buffer input after the Pattern Generation Timing and Control module gives the data the selected data position and data delay. The buffer converts the data signal to LVDS voltage levels before sending the data signal to the DDC connector on the NI 656x front panel.

The buffer can be set to high-impedance generation with the tristate control line. The tristate control cannot be set automatically by the Initial and Idle States. Set tristate programmatically with the niHSDIO Tristate Channels VI or niHSDIO_TristateChannels function.

Protection for the channel electronics is critical for guarding against overvoltage situations and is built into the LVDM buffers. Refer to Input Protection for more information about this portion of the channel electronics.

Note  LVDM buffers drive LVDS logic levels across 100 Ω source and 100 Ω destination termination loads (50 Ω total DC load).

Dynamic Acquisition

Patterns acquired by the NI 656x are received using a differential receiver. Refer to the NI 656x Specifications for the input voltage thresholds and ranges for LVDS.

The output of the receiver is sampled by the Pattern Acquisition Timing and Control module before being sent to the Pattern Acquisition Engine for storage into Acquisition Memory.

The input impedance is differential 100 Ω.