Integration and System Considerations
System Reference Clock, PXI_CLK10

The PXI chassis supplies the PXI 10 MHz system Reference clock signal (PXI_CLK10) independently to each peripheral slot. An independent buffer drives the clock signal to each peripheral slot. The buffer has a source impedance matched to the backplane and a skew ranging from less than 1 ns to better than 250 ps between slots. You can use this common Reference clock signal to synchronize multiple devices in a measurement or control system. You can drive PXI_CLK10 from an external source through the PXI_CLK10_IN pin on the P2 connector of the PXI Star trigger slot, which is slot 2. Sourcing an external clock on this pin automatically disables the 10 MHz source on the backplane. You can synchronize multiple chassis that have connectors on the back panel for 10 MHz reference in and 10 MHz reference out. Refer to your PXI chassis documentation for more information.