NI 5402/5406/5412/5421/5422/5441
Exporting Signals
The signal generator contains seven PXI trigger lines or seven RTSI (PCI devices only) lines that are available for sending signal generator-specific information to other devices that have PXI trigger or RTSI bus connectors. The signal generator also connects to the PXI Star trigger line, which you can use to send or receive signals to or from the PXI Star trigger line on an NI 6653 system timing and control module (Slot 2 controller).
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Note For more information about the NI 6653 system timing and control module, visit ni.com/products. |
The signal generator has connectors on the front panel to route signals to devices external to the PXI or PCI chassis. The following table shows the signals available for export and the lines they can be routed to. To determine all possible signal routes for your device, refer to Signal Routing.
| Destination | ||||
|---|---|---|---|---|
| PXI Bus, PXI_Trig<0..6>, RTSI Bus, RTSI<0..6>, or PXI_STAR |
SYNC OUT/PFI 0 and PFI 1 Connectors |
PFI<4..5>* on DIGITAL DATA & CONTROL Connector |
||
| Exported Clocks, Triggers, and Events | Sample Clock | Yes |
Yes** |
– |
| Sample Clock Timebase*** | Yes |
Yes |
– |
|
| PLL Reference Source | Yes |
Yes** |
– |
|
| Out Start trigger | Yes |
Yes |
Yes |
|
| Marker Event | Yes |
Yes*** |
Yes |
|
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*Note Devices without a DDC connector are not supported. **Note SYNC OUT/PFI 0 is optimized for the Sample clock and PLL reference source signals and has slightly less jitter than PFI 1. SYNC OUT/PFI 0 is the recommended terminal to use for exporting clocks. ***Note This configuration is not supported on the NI 5402/5406. |
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Sample Clock–The clock signal that tells the DAC when to convert the digital waveform values to an analog voltage. The Sample clock frequency is referred to as the Sample clock rate; the rate at which the digital waveforms from device memory are generated. The Sample clock is also known as update clock.
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Notes The Sample clock can be exported directly, or it can first be divided down by an integer. This configuration provides a variable frequency signal related to the waveform sample rate to synchronize other devices to the generation. |
| NI does not recommend exporting clocks greater than 20 MHz over PXI_TRIG<0..6> or RTSI<0..6>. | |
| If you export the divided-down Sample clock to another device to synchronize sampling, you can also use the Sample clock as the Start trigger for the signal generator. Using the divided-down Sample clock as the Start trigger begins signal generation at the same place each time relative to the divided-down Sample clock. This technique is more useful as the divisor becomes larger and, while an improvement over using an immediate Start trigger, there remains an uncertainty of one Sample clock. |
Sample Clock Timebase–The clock signal from which the internal Sample clock is derived. For the NI 5402/5406/5412/5421/5441, the Sample clock timebase is 100 MHz; for the NI 5422, the Sample clock timebase is 200 MHz. The Sample clock timebase is also know as board clock.
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Note The Sample clock timebase (board clock) is always exported after being divided-down. The default divide-down value is 2 for the NI 5412/5421/5441 and 4 for the NI 5422. Valid divide-down values range from 2 to 4,194,304 for the NI 5412/5421/5441 and 4 to 4,194,304 for the NI 5422. |
| If you export the Sample clock timebase to another device to synchronize sampling, you can also use the Sample clock timebase as the Start trigger for the signal generator. Using the Sample clock timebase as the Start trigger begins signal generation at the same place each time relative to the Sample clock timebase. This technique is more useful as the divisor becomes larger and while an improvement over using an immediate Start trigger there remains an uncertainty of one Sample clock. |
PLL Reference source–A clock signal that is only available when a PLL Reference source has been configured. The clock is the source selected as the PLL Reference Clock source.
Out Start trigger–A signal generated by the device upon recognizing a start condition that can be routed out various connectors to signal other devices.
Marker event–A digital signal that can be used as a trigger corresponding to a specific sample in the waveform generation. This signal controls other devices that require timing information related to a specific point in the generated waveform.
Routing Signals
You can route signals in the following ways:
- The Marker event generated during an Arbitrary Waveform Generation mode waveform generation to any of the PXI trigger lines, RTSI lines (PCI devices only), PXI_STAR, or front panel connectors.
- The signal generator Start trigger output signal to other devices through any of the PXI trigger lines, RTSI lines (PCI devices only), PXI_STAR, or front panel connectors.
- The signal generator Sample clock signal to other devices through any of the PXI trigger lines, RTSI lines (PCI devices only), PXI_STAR, or front panel connectors.
- The PLL Reference clock source to other devices through any of the PXI trigger lines, RTSI lines (PCI devices only), PXI_STAR, or front panel connectors.
In NI-FGEN, the PXI trigger lines are referred to as RTSI<0..6>. The correlation between PXI_TRIG<x> and RTSI<x> is one to one. For more information about configuring and routing the device internal signals, refer to the niFgen Export Signal VI or the niFgen_ExportSignal function.