NI 5412/5421/5422/5441/5442
Phase-Locked Loop Reference Clock

A phase-locked loop (PLL) is a circuit that tunes the Sample clock timebase to phase–lock to an external Reference clock. The frequency stability and accuracy of the Sample clock timebase matches that of the Reference clock when they are phase–locked. Using the PLL on your device enables you to frequency-lock multiple devices in a single chassis or devices in separate chassis.

Note  Refer to the device specifications for information about the phase-locked loop reference frequencies available on your device.

The following figure shows the NI 5412/5421/5422/5441/5442 Reference Clock Source path.

Legend

To begin the PLL, the phase comparator compares the selected Reference clock to the 100 MHz (or 200 MHz for the NI 5422) clock of the Sample clock timebase. Next, a control voltage proportional to the phase difference between the two clocks is developed and used to tune the Sample clock timebase into alignment with the Reference clock. Finally, the Sample clock timebase output is routed back to the phase comparator, closing the loop.

Note  When the Reference Clock Source property or the NIFGEN_ATTR_REFERENCE_CLOCK_SOURCE attribute is set to "None"; the internal calibration DAC generates the calibration voltage, and the PLL circuit is not used.

Reference Clock Sources

The NI 5412/5421/5422/5441/5442 can phase–lock its Sample clock timebase to an external signal that is present on the CLK IN front panel connector. PXI devices can also phase–lock to a 10 MHz Reference clock signal provided by the PXI bus (PXI_CLK10), while PCI devices can phase–lock to RTSI line 7 or to the onboard Reference clock.

The following table is a subset of the table in Sample Clock Sources, and shows the valid NI-FGEN property value combinations that can be used to configure the NI 5412/5421/5422/5441/5442 clock settings for an external Reference clock. The attributes that correspond to these properties are NIFGEN_ATTR_SAMPLE_CLOCK_SOURCE, NIFGEN_ATTR_CLOCK_MODE, and NIFGEN_ATTR_REFERENCE_CLOCK_SOURCE. The valid attribute value combinations will reflect the valid property combinations.

Sample Clock Source	Clock Mode	PLL Reference Clock Source
"OnboardClock" (default)	NIFGEN_VAL_DIVIDE_DOWN	"None"
		"PXI_CLK10", "RTSI7"
		"ClkIn", "RefIn"
		"OnboardRefClk"
	NIFGEN_VAL_HIGH_RESOLUTION	"None"
		"PXI_CLK10", "RTSI7"
		"ClkIn", "RefIn"
		"OnboardRefClk"
	NIFGEN_VAL_AUTOMATIC (default)	"None"
		"PXI_CLK10", "RTSI7"
		"ClkIn", "RefIn"
		"OnboardRefClk"

Note  Refer to the device specifications for information about available signal levels on the CLK IN front panel connector.

Refer to the niFgen Configure Reference Clock VI or the niFgen_ConfigureReferenceClock function for more information about configuring the Reference clock.