NI PXI/PCI-5422
Internal Sample Clock

The NI 5422 can derive a Sample clock from its main internal timing source—the Sample clock timebase. The signal generator provides a high-precision 200 MHz Voltage Controlled Crystal Oscillator (VCXO) clock source for the Sample clock timebase. As shown in the following figure, the Sample clock timebase frequency is tuned by an Internal Calibration DAC control voltage when the Reference Clock Source property or the NIFGEN_ATTR_REFERENCE_CLOCK_SOURCE attribute is set to "None". The Internal Calibration DAC, which is calibrated at the factory and which you can also calibrate, provides for the Sample clock timebase to maintain a high quality frequency source.

There are two methods, referred to as clock modes, for creating the Sample Clock: Divide-Down (Divide by N) Sampling and High-Resolution Sampling.

In Divide-Down Sampling mode, the Divide by N circuit uses the Sample clock timebase of 200 MHz to create the frequency available for use as the Sample clock. Divide-Down Sampling mode can generate any Sample clock frequency of 200 MHz/N, where N is any integer from 1 to 40. The Divide-Down Sample clock can run at 200 MHz, 100.0 MHz, 66.66 MHz, 50.0 MHz, 40.0 MHz, 33.332 MHz, and so on. The low frequency limit in Divide-Down Sampling mode is 5 MHz (200 MHz/40). Divide-Down Sampling mode provides a high-quality clock with the lowest jitter.

The High-Resolution Sampling mode also uses the Sample clock timebase at 200 MHz to generate a frequency from 5 MHz to 200 MHz. In addition, the High-Resolution mode uses direct digital synthesis to generate very fine resolution increments on the order of microhertz. Refer to the NI 5422 specifications for more information.

The following table, a subset of the table in Sample Clock Sources, shows the valid NI-FGEN property or attribute values and combinations to configure the NI 5422 clock settings for an internal Reference clock. Refer to niFgen Configure Clock Mode VI or niFgen_ConfigureClockMode function for more information about setting up the clock.

Sample Clock Source	Clock Mode	PLL Reference Clock Source
"OnboardClk" (default)	NIFGEN_VAL_DIVIDE_DOWN	"None" (default)
	NIFGEN_VAL_HIGH_RESOLUTION
	NIFGEN_VAL_AUTOMATIC (default)

You can specifically set the clock mode for either Divide-Down Sampling or High-Resolution Sampling. Alternatively, you can select Automatic mode, which has NI-FGEN switch between the Divide-Down Sampling and High-Resolution Sampling mode, depending on the configured Sample Rate. NI-FGEN chooses the Divide-Down Sampling mode if the configured frequency exactly matches one of the possible divide-down frequencies. If the configured frequency does not match one of the possible divide-down frequencies, the High-Resolution Sampling mode is selected to provide the Sample clock frequency.

Note  The jitter of the High-Resolution clocking mode is frequency dependent. Refer to the NI 5422 specifications for more information.