NI 5412/5421/5422/5441/5442
CLK IN Connector

The CLK IN front panel connector can accept an external Reference clock or external Sample clock.

Caution  Do not change the external clocks while generating waveforms. Only modify the frequency of the external clock before you start the waveform generation or after you stop the waveform generation. NI cannot guarantee the quality of the generated signal if you change the external clock during waveform generation.

External Reference Clock Input

The CLK IN connector can accept a Reference clock from an external source and phase lock the internal clock of the signal generator to this external Reference clock. Refer to the device specifications for the allowable Reference clock frequencies and signal characteristics.

The Reference clock uses the internal clock by default. Refer to the niFgen Configure Reference Clock VI or the niFgen_ConfigureReferenceClock function for more information about configuring the Reference clock source.

When configuring an external Reference clock, you must configure the external Reference clock frequency if it is different from the 10 MHz default setting. Refer to the niFgen Configure Reference Clock VI or the niFgen_ConfigureReferenceClock function for more information about configuring the Reference clock frequency.

Note  You also can phase–lock the signal generator to other NI devices using the common PXI 10 MHz backplane clock on PXI devices or the RTSI 7 line on PCI devices. Refer to PLL Reference Sources for more information about configuring the Reference clock.

External Sample Clock Input

In addition to phase-locking, the CLK IN connector also can receive an external Sample clock. Refer to the device specifications for the allowable external Sample clock frequencies and signal characteristics.

Caution  When configuring an external Sample clock, set the sample rate to the exact frequency you are using to avoid data errors. Refer to the niFgen Set Sample Rate VI or niFgen_ConfigureSampleRate function for more information about setting the sample rate.

You can configure the Sample clock source with niFgen Configure Sample Clock Source VI or the niFgen_ConfigureSampleClockSource function. The Sample clock uses the internal clock by default.