Clocking

Divide-Down Clocking

Divide-down clocking uses the Sample Clock Timebase—the main timing component—of the device. This component is usually a voltage–controlled crystal oscillator (VCXO). The valid sample rates for divide-down clocking are integer divisions of the Sample Clock Timebase frequency. The sample rate is given by the formula:

SR = SCTF/n

where

SR = sample rate

n = integer from 1 to a maximum value for the specific device

SCTF = Sample clock timebase frequency for the specific device

For example, for a signal generator with a Sample clock timebase frequency of 100 MS/s, SCTF = 100 MS/s, and the available sample rates are integer divisions of 100 MS/s, as shown in the following examples:

SCTF/1 = 100 MS/s

SCTF/2 = 50 MS/s

SCTF/3 = 33.333 MS/s

As the integer n increases, the available sample rate decreases. If you choose a sample rate other than an integer division of the Sample clock timebase, the device usually coerces the sample rate setting to the nearest sample rate or integer division of the Sample clock timebase.

Divide-down clocking provides the lowest jitter Sample clock, and is also referred to as /N or divide by n clocking.

High-Resolution Clocking

High-resolution clocking allows you to set the Sample clock frequency to any value from zero to the device Sample clock timebase frequency with a very fine resolution typically in the millihertz or microhertz range. This mode is useful for applications that require a precise clock source, which is not possible using the divide-down clocking scheme.

High-resolution clocking has more jitter than divide-down clocking.

External Clocking

External clocking allows you to connect an external clock to the NI signal generator. This external clock can then be used as the Sample clock for the device.