NI 5402/5406/5412/5421/5422/5441/5442
Power-Up and Reset Conditions

The signal generator is in the following state from when the computer begins to power up until the operating system is fully booted and NI-FGEN is loaded.

• The CH 0 analog output connector is disabled and has 50 Ω or 75 Ω impedance to ground. This impedance is the same as its previous setting before the device was powered down. Also, the output voltage amplitude of this connector is 0 V.
• CLK IN and REF IN connectors have 50 Ω impedance to ground.
• PFI 0, SYNC OUT/PFI 0, and PFI 1 are tristated and have a 1 kΩ impedance to ground.
• In devices with a DDC connector, DIGITAL DATA & CONTROL output lines are disabled and floating; inputs have a 100 Ω differential termination.
• PXI trigger or RTSI lines are tristated and floating.

After the operating system is fully booted and NI-FGEN is loaded, or when you perform a hard reset to the device directly from MAX or using NI-FGEN, the signal generator is in the following state:

• CH 0 output is enabled.
• CH 0 output attenuation is set to 0 dB.
• Output impedance is set to 50 Ω.
• The Low-Gain Amplifier path is enabled in the Analog Output path.
• The analog filter is disabled.
• The digital filter of the NI 5402/5406/5412/5421/5441/5442 inside the DAC is disabled.
• CLK IN or REF IN is disabled and has a 50 Ω impedance to ground.
• PFI 0, SYNC OUT/PFI 0, and PFI 1 are tristated and have a 1 kΩ impedance to ground.
• On applicable devices, all output lines on the DIGITAL DATA & CONTROL Connector are disabled and floating; inputs have a 100 Ω differential termination.
• PXI trigger or RTSI lines are tristated and floating.
• The sample rate is set to the maximum rate, with the Sample clock source set to the internal Sample clock timebase.
• The Sample clock timebase is tuned by the internal reference control voltage.