NI 5412/5421/5441/5442
Internal Sample Clock

The NI 5412/5421/5441/5442 can derive a Sample clock from its main internal timing source—the Sample Clock Timebase. The signal generator provides a high-precision 100 MHz Voltage Controlled Crystal Oscillator (VCXO) clock source for the Sample Clock Timebase. As shown in the following figure, the Sample Clock Timebase frequency is tuned by an Internal Calibration DAC control voltage when the Reference Clock Source property or the NIFGEN_ATTR_REFERENCE_CLOCK_SOURCE attribute is set to "None". The Internal Calibration DAC, which is calibrated at the factory and which you also can calibrate, provides for the Sample Clock Timebase to maintain a high quality frequency source.

There are two methods, referred to as clock modes, for creating an internal Sample clock from the Sample Clock Timebase: Divide-Down (Divide by N) Sampling and High-Resolution Sampling.

In Divide-Down Sampling mode, the Divide by N circuit uses the Sample clock timebase of 100 MHz to create the frequency available for use as the Sample clock. Divide-Down Sampling mode can generate any internal timebase frequency of 100 MHz/N, where N is any integer from 1 to 4,194,304. For example, the internal timebase can run at 100 MHz, 50.0 MHz, 33.33 MHz, 25.0 MHz, 20.0 MHz, 16.666 MHz, and so on. The low frequency limit in Divide-Down Sampling mode is 23.84185 (100 MHz/4,194,304) Hz. Divide-Down Sampling mode provides a high-quality clock with the lowest jitter.

The High-Resolution Sampling mode also uses the Sample clock timebase at 100 MHz to generate a frequency from 10 Hz to 100 MHz. In addition, the High-Resolution mode uses direct digital synthesis to generate very fine resolution increments on the order of microhertz. Refer to the module specifications for more information.

The following table, a subset of the table in Sample Clock Sources, shows the valid NI-FGEN property or attribute value combinations that can be used to configure the NI 5412/5421/5422/5441/5442 clock settings for an internal Sample clock. Refer to the niFgen Configure Clock Mode VI or the niFgen_ConfigureClockMode function for more information about setting up the clock.

Sample Clock Source	Clock Mode	PLL Reference Clock Source
"OnboardClk" (default)	NIFGEN_VAL_DIVIDE_DOWN	"None" (default)
	NIFGEN_VAL_HIGH_RESOLUTION
	NIFGEN_VAL_AUTOMATIC (default)

You can specifically set the clock mode for either Divide-Down Sampling or High-Resolution Sampling. Alternatively, you can select Automatic mode, which has NI-FGEN switch between the Divide-Down Sampling and High-Resolution Sampling mode, depending on the configured sample rate. NI-FGEN chooses the Divide-Down Sampling mode if the configured frequency exactly matches one of the possible divide-down frequencies. If the configured frequency does not match one of the possible divide-down frequencies, the High-Resolution Sampling mode is selected to provide the Sample clock frequency.

Note  The jitter of the High-Resolution clocking mode is frequency–dependent. At low frequencies the jitter increases. Refer to the device specifications for more information.