Phase-Locked Looping

A phase–lock loop (PLL) is a circuit that adjusts a main clock to synchronize to a Reference clock. The frequency stability of the Sample clock timebase matches that of the Reference clock when the two are phase–locked. Phase locking also synchronizes clocks of multiple devices that are phase–locked to the same Reference clock.

The following figure shows a block diagram of a basic PLL.

The operation of this circuit is typical of all PLLs. A PLL is a feedback control system that controls the phase of a voltage–controlled oscillator (VCO). The frequency reference signal is applied to a phase detector. The output of the VCO connects to the other input. Normally the frequencies of both signals are almost the same. The output of the phase detector has a voltage proportional to the phase difference between the two input signals. The loop filter receives this signal from the phase detector. The loop filter determines the dynamic characteristics of the PLL.