NI 5421/5422/5441/5442
Sample Clock
Waveform generation is driven by the Sample clock; depending on your application, some sources may be better choices than others. You can use the following sources for the NI 5421/5422/5441/5442 Sample clock:
- Internal Sample clock—the Sample clock is derived from the Sample clock timebase via either Divide by N or High-Resolution clock mode.
- External Sample clock—the Sample clock is driven directly from an external source.
- Reference clock—the Sample clock is derived from an external source that is phase-locked to the Sample clock timebase.
The following table shows the valid NI-FGEN property or attribute value combinations that can be used to configure the NI 5412/5421/5422/5441/5442 clock settings for an internal Sample clock, an external Sample clock, or a Reference clock. The term Update clock is synonymous with Sample clock.
| Sample Clock Source* | Clock Mode* | PLL Reference Clock Source* |
|---|---|---|
| "OnboardClk" (default) | NIFGEN_VAL_DIVIDE_DOWN | "None" |
| "PXI_CLK10", "RTSI7" | ||
| "ClkIn", "RefIn" | ||
| "OnboardRefClk" | ||
| NIFGEN_VAL_HIGH_RESOLUTION | "None" | |
| "PXI_CLK10", "RTSI7" | ||
| "ClkIn", "RefIn" | ||
| "OnboardRefClk" | ||
| NIFGEN_VAL_AUTOMATIC (default) | "None" | |
| "PXI_CLK10", "RTSI7" | ||
| "ClkIn", "RefIn" | ||
| "OnboardRefClk" | ||
| "ClkIn" | Not Applicable | Not Applicable |
| "PXI_STAR" | ||
| "PXI_Trig<0..6>" | ||
| "DDC_ClkIn" | ||
| *These column headings refer to NI-FGEN properties. The attributes that correspond to these properties are NIFGEN_ATTR_SAMPLE_CLOCK_SOURCE, NIFGEN_ATTR_CLOCK_MODE, and NIFGEN_ATTR_REFERENCE_CLOCK_SOURCE. The values in the columns represent the values that can be set on these properties or attributes. Settings that line up horizontally show valid combinations of the NI-FGEN settings. | ||
Sample Clock Source
The Sample clock source is the clock from which the Sample clock is derived, and it drives the DAC and all waveform generation operations on the device. You can set the Sample clock source by using the Sample Clock Source property or the NIFGEN_ATTR_SAMPLE_CLOCK_SOURCE attribute. The default NI-FGEN setting for the Sample Clock Source property or the NIFGEN_ATTR_SAMPLE_CLOCK_SOURCE attribute is "OnboardClk." The Sample clock source only requires configuration during applications that require an external Sample clock.
The NI 5421/5422/5441/5442 supports five options for the Sample clock source: one internal and four external sources. The fundamental clock source for your waveform generation application is the Sample clock timebase. The NI 5421/5441/5442 provides a high-precision 100 MHz voltage controlled crystal oscillator (VCXO) internal source from which all waveform generation operations are derived. The NI 5422 provides a high-precision 200 MHz VCXO internal source. The external sources are the NI 5421/5422/5441/5442 CLK IN front panel connector, DDC CLK IN on the DIGITAL DATA & CONTROL front panel connector (not available on the 5442), PXI_STAR, PXI_Trig<0..6> (PXI devices only), and the RTSI<0..6> (PCI devices only) lines.
For more information about configuring the Sample clock source for an external Sample clock, refer to External Sample Clock Sources.
Clock Mode
The clock mode determines the method of deriving the Sample clock from the Sample clock timebase. You can set the clock mode with the Clock Mode property or the NIFGEN_ATTR_CLOCK_MODE attribute. The clock mode is only applicable when using an internal Sample clock.
There are three options for setting the clock mode on your NI 5421/5422/5441/5442: Divide-Down (Divide by N) Sampling, High-Resolution Sampling, and Automatic mode. The default NI-FGEN setting for the clock mode is Automatic. The Automatic mode setting switches between the Divide-Down and the High-Resolution mode depending on the sample rate configured with the Sample Rate property or the NIFGEN_ATTR_ARB_SAMPLE_RATE attribute.
For more information about configuring the clock mode, refer to Internal Sample Clock Sources.
PLL Reference Clock Source
The phase-locked loop (PLL) Reference clock source specifies the source of the control voltage that tunes the VCXO of the Sample clock timebase for internal clock update sources. The PLL circuit adjusts the Sample clock timebase VCXO to synchronize to a Reference clock.
The frequency stability of the Sample clock timebase matches that of the PLL Reference clock when the two are phase-locked. Phase-locking also synchronizes multiple device clocks that are phase–locked to the same Reference clock.
You can set the PLL Reference clock source with the Reference Clock Source property or the NIFGEN_ATTR_REFERENCE_CLOCK_SOURCE attribute. There are five options for selecting the PLL Reference clock source on the NI 5421/5422/5441/5442: "None", "PXI_CLK10" (PXI), "RTSI7" (PCI), "OnboardRefClk" (PCI), and "ClkIn". The default NI-FGEN setting for the Reference Clock Source property or the NIFGEN_ATTR_REFERENCE_CLOCK_SOURCE attribute is "None".
For more information about the NI 5421/5422/5441/5442 PLL circuit, refer to PLL Reference Sources.