NI 5421/5422/5441/5442
Exporting Clocks

The NI 5421/5422/5441/5442 provides two resources for exporting your clocks and multiple destinations for routing.

The following table shows the available clock signals that can be routed to devices external to the NI 5421/5422/5441/5442 and the destination options.

Sample Clock

For synchronization purposes, the NI 5421/5422/5441/5442 allows you to export your Sample clock so that other devices can have the same timing as the NI 5421/5422/5441/5442. The Sample clock can be routed to the PFI <0..1> front panel SMB connectors, PXI_Trig<0..6> lines on the PXI trigger bus, or the RTSI<0..6> lines. Additionally, the Sample clock has a direct route to the DDC CLK OUT line on the DIGITAL DATA & CONTROL connector on the front panel (not available on the NI 5442).

Additionally, the exported clock can be divided down by an integer value (no less than 2) before being exported to the PFI<0..1> SMB connectors, PXI_Trig<0..6> lines, or the RTSI<0..6> lines. Refer to the Exported Sample Clock Divisor property or the NIFGEN_ATTR_EXPORTED_SAMPLE_CLOCK_DIVISOR attribute for more information about configuring the Sample clock divisor.

Sample Clock Timebase

For synchronization purposes, the NI 5421/5422/5441/5442 allows you to export your Sample clock timebase so that other devices can have the same timing as the signal generator. The Sample clock timebase can be routed to the PFI <0..1> SMB connectors on the front panel, the PXI_Trig<0..6> lines on the PXI trigger bus, or the RTSI<0..6> lines. Additionally, the Sample clock timebase has a direct route to the DDC CLK OUT line on the DIGITAL DATA & CONTROL connector on the front panel (not available on the NI 5442).

Additionally, the exported clock can be divided down by an integer value before being exported to the PFI<0..1> SMB connectors, the PXI_Trig<0..6> lines, or the RTSI<0..6> lines. Refer to Exported Sample Clock Timebase Divisor property or the NIFGEN_ATTR_EXPORTED_SAMPLE_CLOCK_TIMEBASE_DIVISOR attribute for more information about configuring the Sample clock divisor.

Reference Clock

For synchronization purposes, the NI 5421/5422/5441/5442 allows you to export your PLL Reference clock so that other devices can lock their clock sources to the same signal. Referring to the previous image, this clock is the actual clock that is configured for the NI 5421/5422/5441/5442 phase-locked loop circuit to use as a reference. You configure a Reference clock as a PLL Reference clock source for the signal to be available for exporting. The Reference clock can be routed to the PFI<0..1> SMB connectors on the front panel, the PXI_Trig<0..6> lines on the PXI trigger bus, or the RTSI<0..6> lines.

Note  Although NI-FGEN allows values for Reference clock frequency on the NI 5421/5422/5441/5442 from 1 MHz to 20 MHz in 1 MHz increments, the NI 5421/5422/5441/5442 specifications are only valid with Reference clock frequencies from 5 MHz to 20 MHz.

Onboard Reference Clock

The onboard Reference clock is a dedicated 10 MHz clock for PCI modules only. The onboard Reference clock can only be exported to RTSI7, for other devices to use and reimport as the Reference clock.

Tip  By exporting the onboard Reference clock and then reimporting it, all devices (including the master) can use the same Reference clock.

Destination Options

The following sections define the destinations for exported clocks.

DDC CLK OUT—You can export the Sample clock to the DDC CLK OUT line on the DIGITAL DATA & CONTROL (DDC) connector (not available on the NI 5442). Exporting the clock from this connection allows for synchronous clocking of the DDC data. You must enable the DDC connector before using the Sample clock. Refer to the niFgen Configure Digital Patterning VI or the niFgen_EnableDigitalPatterning and niFgen_DisableDigitalPatterning functions for more information about enabling the DDC connector.

PFI <0..1>—The Sample clock and the Reference clock can be exported to the PFI 0 and PFI 1 SMB connectors on the front panel to synchronize external devices. You must configure the device to export the desired clock to the PFI SMB connectors.

Note  PFI 0 is optimized to have lower jitter than PFI 1 for exporting the Sample clock or the Reference clock.

PXI_Trig<0..6>—The Sample clock and the Reference clock can be exported to the PXI_Trig lines or RTSI lines. The PXI and PCI standards allow for devices to route signals to other devices in your PXI chassis to enhance device to device synchronization. Refer to the chassis documentation for specifications to ensure the reference signal is within tolerance. You must configure the device to export the desired clock to the PXI_Trig line or RTSI line. When exporting signals, the following lines are equivalent:

• PXI_Trig<0..6> = RTSI_<0..6>
• PXI_STAR

Refer to niFgen Export Signal VI or the niFgen_ExportSignal function for more information about configuring the destinations for the desired clock signal.