documentation
.HELP!
NI Signal Generator Documentation
NI PXI-5404 Block Diagram
NI Signal Generator
previous page
next page
NI PXI-5404
Block Diagram
The following figure shows the NI PXI-5404 block diagram.
previous page
start
next page
Menu
Homepage
Table of contents
NI Signal Generators Help
Related Documentation
Using Help
Conventions
Navigating Help
Searching Help
Printing Help File Topics
Fundamentals
Waveform Fundamentals
Bandwidth and Flatness
Sample Rate
Nyquist and Shannon's Sampling Theorems
Aliased Images
DAC Resolution
Arbitrary Waveform Generation Mode
Digital Pattern Generation
Marker Output Signal
Minimum Waveform Size and Quantum
Standard Function Mode
Direct Digital Synthesis (DDS)
Frequency Hopping and Sweeping
Clocking
Impedance Matching
Output Attenuation
Output Enable
Output Impedance
Phase-Locked Looping
Triggering
Triggers Summary
Types of Triggers
Edge Trigger
Level Trigger
Software Triggers
Trigger Modes
Trigger Sources
Events
Marker Events
Data Marker Events
Scripts
Streaming
Direct DMA
Frequency Domain Fundamentals
SFDR
THD
SINAD
ENOB
Filtering and Interpolation
Devices
NI 5401/5404/5411/5431 Features Supported
NI 5402/5406/5412/5421/5422/5441 Features Supported
NI 5401
Front Panel Connectors
ARB
PLL Ref
Pattern Out (PCI Only)
SHC50-68 50-Pin Cable Connector
SYNC
LOCK and ACCESS LEDs
Power-Up and Reset Conditions
Theory of Operation
Block Diagram
Analog Output Path
Output Attenuation
Analog Filter Correction
Output Enable
DDS Lookup Memory
Waveform Generation
Frequency Hopping and Sweeping
Triggering
Trigger Sources
RTSI/PXI Trigger Lines
Trigger Modes
Burst/Stepped
Single Trigger Mode
Continuous Trigger Mode
Phase-Locked Loops and Module Synchronization
Specifications
Calibration
Accessories
Connector blocks
NI 5402/5406
NI PXI-5402/5406
Front Panel Connectors
CH 0
REF IN
SYNC OUT/PFI 0 and PFI 1
Access and Active LEDs
Power-Up and Reset Conditions
Thermal Shutdown
Theory of Operation
Block Diagram
Hardware State Diagram
Analog Output Path
Waveform Amplitude Control
DC Offset
Digital Gain
Flatness Correction
Filtering
Analog Filter
Digital Filter
Output Enable
Output Impedance
Clocking
Sample Clock
Reference Clock
Exporting Clocks
Onboard Memory
Signal Routing
Syntax for Terminal Names
Waveform Generation
Standard Function
Frequency List
Frequency Hopping and Sweeping
Trigger Modes
Aborting Generation
Triggering
Trigger Sources
Trigger Modes
Trigger Timing
Filtering Effects
Data Mask
Events
Event Delays
Exporting Signals
Synchronization
Specifications
Calibration
Accessories
NI PCI-5402/5406
Front Panel Connectors
CH 0
REF IN
SYNC OUT/PFI 0 and PFI 1
Power-Up and Reset Conditions
Thermal Shutdown
Theory of Operation
Block Diagram
Hardware State Diagram
Analog Output Path
Waveform Amplitude Control
DC Offset
Digital Gain
Filtering
Analog Filter
Digital Filter
Output Enable
Output Impedance
Clocking
Sample Clock
Reference Clock
Exporting Clocks
Onboard Memory
Signal Routing
Syntax for Terminal Names
Waveform Generation
Standard Function
Frequency List
Trigger Modes
Frequency Hopping and Sweeping
Aborting Generation
Triggering
Trigger Sources
Trigger Modes
Trigger Timing
Filtering Effects
Data Mask
Events
Event Delays
Exporting Signals
Synchronization
Specifications
Calibration
Accessories
NI 5404
Front Panel Connectors
SINE Out
CLOCK Out
PFI 0
REF OUT
REF IN
ACCESS and ACTIVE LEDs
Power-Up and Reset Conditions
Theory of Operation
Block Diagram
Analog Output Path
Locking to a Reference Clock
Phase-Locked Looping
Waveform Generation
Waveform Start Conditions
Generating a Sine Wave
Generating a Clock Signal (Square Wave)
Triggering
Trigger Sources
RTSI/PXI Trigger Lines
Continuous Trigger Mode
Exporting Signals
Phase-Locked Loops and Device Synchronization
Specifications
Calibration
Accessories
NI 5411
Front Panel Connectors
ARB Out
PLL Ref/External Clock
DIGITAL PATTERN
SHC50-68 50-Pin Cable Connector
Digital Pattern Generation
SYNC
Lock and Access LEDs
Power-Up and Reset Conditions
Theory of Operation
Block Diagram
Analog Output Path
Waveform Amplitude Control
Pre-Attenuation Offset
Output Attenuation
Filtering
Analog Filter Correction
Digital Filter Considerations
Output Enable
External and High-Resolution Clocking (PXI only)
Onboard Memory
DDS Lookup Memory
Waveform Memory
Waveform Generation
Arbitrary Waveform Generation
Sample Size and Resolution
Minimum Waveform Size and Resolution
Frequency Hopping and Sweeping
Waveform Staging
Linking and Looping
Marker Events
Triggering
Trigger Sources
RTSI/PXI Trigger Lines
Trigger Modes
Single Trigger Mode
Continuous Trigger Mode
Stepped Trigger Mode
Burst Trigger Mode
Phase-Locked Loops and Module Synchronization
Master/Slave Operation
Events
Marker Events
Specifications
Calibration
Accessories
Installing the Optional Memory Module
NI 5412
NI PXI-5412
Front Panel Connectors
CH 0
CLK IN
PFI 0 and PFI 1
Access and Active LEDs
Power-Up and Reset Conditions
Thermal Shutdown
Theory of Operation
Block Diagram
Hardware State Diagram
Analog Output Path
Waveform Amplitude Control
DC Offset
Digital Gain
Filtering
Digital Filter
Output Enable
Output Impedance
Clocking
Sample Clock
Internal Sample Clock
External Sample Clock
Reference Clock
Exporting Clocks
Onboard Memory
Waveform and Instruction Memory Size
Memory Fragmentation
Signal Routing
Syntax for Terminal Names
Waveform Generation
Standard Function
Arbitrary Waveform Generation
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Arbitrary Sequence
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Aborting Generation
Triggering
Trigger Sources
Trigger Modes
Trigger Timing
Filtering Effects
Data Mask
Events
Event Delays
Marker Events
Exporting Signals
Synchronization
Specifications
Calibration
Accessories
NI PCI-5412
Front Panel Connectors
CH 0
CLK IN
PFI 0 and PFI 1
Power-Up and Reset Conditions
Thermal Shutdown
Theory of Operation
Block Diagram
Hardware State Diagram
Analog Output Path
Waveform Amplitude Control
DC Offset
Digital Gain
Filtering
Digital Filter
Output Enable
Output Impedance
Clocking
Sample Clock
Internal Sample Clock
External Sample Clock
Reference Clock
Exporting Clocks
Onboard Memory
Waveform and Instruction Memory Size
Memory Fragmentation
Signal Routing
Syntax for Terminal Names
Waveform Generation
Standard Function
Arbitrary Waveform Generation
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Arbitrary Sequence
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Aborting Generation
Triggering
Trigger Sources
Trigger Modes
Trigger Timing
Filtering Effects
Data Mask
Events
Event Delays
Marker Events
Exporting Signals
Synchronization
Specifications
Calibration
Accessories
NI 5421
NI PXI-5421
Front Panel Connectors
CH 0
CLK IN
DIGITAL DATA & CONTROL
Data Format (LVDS)
PFI 0 and PFI 1
Access and Active LEDs
Power-Up and Reset Conditions
Thermal Shutdown
Theory of Operation
Block Diagram
Hardware State Diagram
Analog Output Path
Waveform Amplitude Control
DC Offset
Digital Gain
Filtering
Analog Filter
Digital Filter
Output Enable
Output Impedance
Clocking
Sample Clock
Internal Sample Clock
External Sample Clock
Reference Clock
Exporting Clocks
Onboard Memory
Waveform and Instruction Memory Size
Memory Fragmentation
Signal Routing
Syntax for Terminal Names
Waveform Generation
Standard Function
Arbitrary Waveform Generation
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Arbitrary Sequence
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Script
Scripting Instructions
script/end script
generate
repeat/end repeat
if/else/end if
wait
clear
Common Scripting Use Cases
Sample Size and Resolution
Waveform Size and Quantum
Generating Marker Events
Streaming Data
Direct DMA
Aborting Generation
Triggering
Trigger Sources
Trigger Modes
Trigger Timing
Filtering Effects
Data Mask
Events
Event Delays
Marker Events
Data Marker Events
Exporting Signals
Synchronization
Specifications
Calibration
Accessories
NI PCI-5421
Front Panel Connectors
CH 0
CLK IN
DIGITAL DATA & CONTROL
Data Format (LVDS)
PFI 0 and PFI 1
Power-Up and Reset Conditions
Thermal Shutdown
Theory of Operation
Block Diagram
Hardware State Diagram
Analog Output Path
Waveform Amplitude Control
DC Offset
Digital Gain
Filtering
Analog Filter
Digital Filter
Output Enable
Output Impedance
Clocking
Sample Clock
Internal Sample Clock Sources
External Sample Clock Sources
Reference Clock
Exporting Clocks
Onboard Memory
Waveform and Instruction Memory Size
Memory Fragmentation
Signal Routing
Syntax for Terminal Names
Waveform Generation
Standard Function
Arbitrary Waveform Generation
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Arbitrary Sequence
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Script
Scripting Instructions
script/end script
generate
repeat/end repeat
if/else/end if
wait
clear
Common Scripting Use Cases
Sample Size and Resolution
Waveform Size and Quantum
Generating Marker Events
Streaming Data
Direct DMA
Aborting Generation
Triggering
Trigger Sources
Trigger Modes
Trigger Timing
Filtering Effects
Data Mask
Events
Event Delays
Marker Events
Data Marker Events
Exporting Signals
Synchronization
Specifications
Calibration
Accessories
NI 5422
Front Panel Connectors
CH 0
CLK IN
DIGITAL DATA & CONTROL
Data Format (LVDS)
PFI 0 and PFI 1
Access and Active LEDs
Power-Up and Reset Conditions
Thermal Shutdown
Theory of Operation
Block Diagram
Hardware State Diagram
Analog Output Path
Waveform Amplitude Control
DC Offset
Digital Gain
Filtering
Analog Filter
Output Enable
Output Impedance
Clocking
Sample Clock
Internal Sample Clock
External Sample Clock
Reference Clock
Exporting Clocks
Onboard Memory
Waveform and Instruction Memory Size
Memory Fragmentation
Signal Routing
Syntax for Terminal Names
Waveform Generation
Standard Function
Arbitrary Waveform Generation
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Arbitrary Sequence
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Script
Scripting Instructions
script/end script
generate
repeat/end repeat
if/else/end if
wait
clear
Common Scripting Use Cases
Sample Size and Resolution
Waveform Size and Quantum
Generating Marker Events
Streaming Data
Direct DMA
Aborting Generation
Triggering
Trigger Sources
Trigger Modes
Trigger Timing
Filtering Effects
Data Mask
Events
Event Delays
Marker Events
Data Marker Events
Exporting Signals
Synchronization
Specifications
Calibration
Accessories
NI 5431
Front Panel Connectors
VIDEO OUT
SYNC OUT
PLL Ref/External Clock
Video Digital Pattern
SHC50-68 50-Pin Cable Connector
DigiSync
Digital Pattern Generation
Lock and Access LEDs
Power-Up and Reset Conditions
Theory of Operation
Block Diagram
Analog Output Path
Waveform Amplitude Control
Pre-Attenuation Offset
Output Attenuation
Filtering
Analog Filter Correction
Digital Filter Considerations
Output Enable
External and High-Resolution Clocking (PXI Only)
Video Signal Generation
Onboard Memory
DDS Lookup Memory
Waveform Memory
Waveform Generation
Arbitrary Waveform Generation
Sample Size and Resolution
Minimum Waveform Size and Resolution
Frequency Hopping and Sweeping
Frequency Resolution and Lookup Memory in Standard Function Mode
Waveform Staging
Linking and Looping
Marker Events
Triggering
Trigger Sources
RTSI/PXI Trigger Lines
Trigger Modes
Single Trigger Mode
Continuous Trigger Mode
Stepped Trigger Mode
Burst Trigger Mode
Phase-Locked Loops and Module Synchronization
Master/Slave Operation
Events
Marker Events
Specifications
Calibration
Accessories
NI 5441
Front Panel Connectors
CH 0
CLK IN
DIGITAL DATA & CONTROL
Data Format (LVDS)
PFI 0 and PFI 1
Access and Active LEDs
Power-Up and Reset Conditions
Thermal Shutdown
Theory of Operation
Block Diagram
Hardware State Diagram
Analog Output Path
Waveform Amplitude Control
DC Offset
Digital Gain
Filtering
Analog Filter
Digital Filter
Output Enable
Output Impedance
Onboard Signal Processing (OSP)
Components
IQ Rate
Pre-Filtering
Pre-Filter Gain
Pre-Filter Offset
FIR Filter
Interpolation
Overflow
Types
Flat
Raised Cosine
Root Raised Cosine
Gaussian
Custom
CIC Filter
Frequency Response
Gain
Overflow
Numerically Controlled Oscillator (NCO)
IQ Combiner
Basic Properties
OSP Enabled
Data Processing Mode
IQ Rate
Sample Clock Considerations
Using an External Clock with the OSP Block
Carrier Frequency
FIR Filter Type
Common Applications
Arbitrary Waveform Generation
Single-Tone
Quadrature Upconversion
Amplitude Modulation (Double Sideband)
Baseband Interpolation
Clocking
Sample Clock
Internal Sample Clock
External Sample Clock
Reference Clock
Exporting Clocks
Onboard Memory
Waveform and Instruction Memory Size
Memory Fragmentation
Signal Routing
Syntax for Terminal Names
Waveform Generation
Standard Function
Arbitrary Waveform Generation
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Arbitrary Sequence
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Script
Scripting Instructions
script/end script
generate
repeat/end repeat
if/else/end if
wait
clear
Common Scripting Use Cases
Sample Size and Resolution
Waveform Size and Quantum
Generating Marker Events
Frequency List
Frequency Hopping and Sweeping
Trigger Modes
Streaming Data
Direct DMA
Aborting Generation
Triggering
Trigger Sources
Trigger Modes
Trigger Timing
Filtering Effects
Data Mask
Events
Event Delays
Marker Events
Data Marker Events
Exporting Signals
Synchronization
Specifications
Calibration
Accessories
NI 5442
Front Panel Connectors
CH 0
CLK IN
PFI 0 and PFI 1
Access and Active LEDs
Power-Up and Reset Conditions
Thermal Shutdown
Theory of Operation
Block Diagram
Hardware State Diagram
Analog Output Path
Waveform Amplitude Control
DC Offset
Digital Gain
Filtering
Analog Filter
Digital Filter
Output Enable
Output Impedance
Onboard Signal Processing (OSP)
Components
IQ Rate
Prefiltering
Prefilter Gain
Prefilter Offset
FIR Filter
Flat
Raised Cosine
Root Raised Cosine
Filtering and Interpolation
Numerically Controlled Oscillator (NCO)
IQ Combiner
Basic Properties
OSP Enabled
Data Processing Mode
IQ Rate
Sample Clock Considerations
Using an External Clock with the OSP Block
Carrier Frequency
FIR Filter Type
Common Applications
Arbitrary Waveform Generation
Single-Tone Generation
Quadrature Upconversion
Amplitude Modulation (Double Sideband)
Baseband Interpolation
Clocking
Sample Clock
Internal Sample Clock
External Sample Clock
Reference Clock
Exporting Clocks
Onboard Memory
Waveform and Instruction Memory Size
Memory Fragmentation
Signal Routing
Syntax for Terminal Names
Waveform Generation
Standard Function
Arbitrary Waveform Generation
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Arbitrary Sequence
Sample Size and Resolution
Waveform Size and Quantum
Trigger Modes
Generating Marker Events
Script
Scripting Instructions
script/end script
generate
repeat/end repeat
if/else/end if
wait
clear
Common Scripting Use Cases
Sample Size and Resolution
Waveform Size and Quantum
Generating Marker Events
Frequency List
Frequency Hopping and Sweeping
Trigger Modes
Streaming Data
Direct DMA
Aborting Generation
Triggering
Trigger Sources
Trigger Modes
Trigger Timing
Filtering Effects
Data Mask
Events
Event Delays
Marker Events
Data Marker Events
Exporting Signals
Synchronization
Specifications
Calibration
Accessories
Integration and System Considerations
Environment
PXI/PXI Express Systems
PXI/PXI Express Chassis Cooling
Modules
PXI Modules
PXI Express Modules
PXI Star Trigger Line
PXI Trigger Lines
System Reference Clock
PFI Lines
MXI Optimization
PCI Systems
Chassis Cooling
RTSI Trigger Lines
PFI Lines
Synchronization
Interactive Tools
FGEN Soft Front Panel
Function Library
Waveform File Specifications
Binary Waveform Data Format (.bin)
Frequency Shift-Keying Source File Specifications
LabVIEW Measurement Data File (.lvm)
Example Files
NI Video Generator Wizard Help
Loading BMP Files and Computing Video
Generating a Video Signal
Editing Video Parameters
Editing Factory Settings
Use Custom Settings
Editing Custom Settings
Downloading and Saving a Video Data File
Downloading a Video Data File
Saving Video Data File to Disk
Saving and Downloading
Loading a Video Data File from Disk
Programming
NI-FGEN Help
Programming State Model
Programming Flow
Simulation Mode
Error Codes
Creating an Application with NI-FGEN and Your ADE
Creating an Application with LabVIEW
Considerations for Using the LabVIEW Real-Time Module
Creating an Application with LabWindows/CVI
Creating an Application with Visual C/C++
Creating an Application with Visual Basic
NI-FGEN Visual C++ Reference Help
NI-FGEN Examples for Measurement Studio
Scripting Instructions
script/end script
generate
repeat/end repeat
if/else/end if
wait
clear
How the NI Video Software Toolkit Filters Video Components
Operating System Support
Glossary
Important Information
Warranty
Copyright
Trademarks
Patents
Warning Regarding the Use of NI Products
Technical Support and Professional Services
Get in touch
Submit feedback about this site to:
[email protected]
