NI PXI/PCI-5411/5431
(Video) Digital Pattern Connector
(Video) Digital Pattern Connector
(VIDEO) DIGITAL PATTERN is a 16-bit digital I/O connector that contains the 16-bit digital pattern outputs, digital pattern clock output, marker output, external trigger input, and +5 V power output.
Refer to SHC50-68 50-Pin Cable Connector for information about adapting the connector from 50 to 68 pins.
NI 5411/5431 DIGITAL PATTERN Pin Assignments
The following figure shows the NI 5411/5431 (VIDEO) DIGITAL PATTERN 50-pin VHDCI female connector.
The following table lists the pin names and signal descriptions used for the NI 5411/5431 (VIDEO) DIGITAL PATTERN connector.
| Signal Name | Type | Description |
|---|---|---|
| DGND | — | Digital ground. |
| EXT_TRIG | Input | External trigger—The external trigger input signal is a TTL-level signal that you can use to start or step through a waveform generation. Refer to Triggering for more information. |
| MARKER | Output | Marker—A marker is a TTL-level output signal that you can set up at any point in the waveform generating. You can use this signal to synchronize or trigger other devices at a certain time within waveform generation. |
| NC | — | Not connected. |
| PA<0..15> | Output | Digital pattern outputs—The 16-bit digital representation of the analog waveform is available on these output pins as digital pattern outputs along with the PCLK signal to which it is synchronized. This data is available directly from the memory after some Sample clocks pipeline delay. The digital pattern outputs are TTL output levels. |
| PCLK | Output | Digital pattern clock—The digital pattern clock output synchronizes the digital pattern output. This data is available directly from the memory after some Sample clocks pipeline delay. The PCLK output is a TTL output level. |
| RFU | — | Reserved for future use. Do not connect signals to this pin. |
| +5V | Output | +5 V power—A +5 V output signal is available on the NI 5411/5431 to power external devices. The maximum current you can draw is 100 mA. |
| NI 5431 Exceptions | ||
|---|---|---|
| Signal Name | Type | Description |
| PA<0> | Output | Vertical Sync (Vsync)k— The portion of the video signal that tells the display where to place the image in the top-to-bottom dimension. |
| PA<1> | Output | Horizontal Sync (Hsync)k— The portion of the video signal that tells the display where to put the picture in the left-to-right dimension. |
| PA<2> | Output | Composite Sync (Csync)k— Composite Synchronization signal; a single signal including both horizontal and vertical synchronization pulses. |
| PA<3> | Output | Field Identification (Field ID)k— The field ID signal identifies the even or odd field in an interlaced video frame. |
| PA<4..15> | Output | Digital pattern outputs—The 12-bit digital representation of the analog waveform is available on these output pins as digital pattern outputs along with the PCLK signal to which it is synchronized. This data is available directly from the memory after some Sample clocks pipeline delay. The digital pattern outputs are TTL output levels. |