NI 5412
Sample Clock
Waveform generation is driven by the Sample clock and, depending on your application, some sources may be better choices than others. You can use the following sources for the NI 5412 clock to derive the Sample clock:
- Internal Sample Clock—the Sample clock is derived from the Sample clock timebase via either divide by N or High-Resolution clock mode.
- External Sample Clock—the Sample clock is driven directly from an external source.
- Reference Clock—the Sample clock is derived from an external source that is phase-locked to the Sample clock timebase.
The following table shows the valid NI-FGEN property or attribute value combinations that can be used to configure the NI 5412/5421/5422/5441/5442 clock settings for an internal Sample clock, an external Sample clock, or a Reference clock. The term Update clock is synonymous with Sample clock.
| Sample Clock Source* | Clock Mode* | PLL Reference Clock Source* |
|---|---|---|
"OnboardClock" (default) |
NIFGEN_VAL_DIVIDE_DOWN |
"None" |
"PXI_CLK10" (PXI), "RTSI7" (PCI) |
||
"ClkIn" / "RefIn" |
||
"OnboardRefClk" (PCI) |
||
NIFGEN_VAL_HIGH_RESOLUTION |
"None" |
|
"PXI_CLK10" (PXI), "RTSI7" (PCI) |
||
"ClkIn" / "RefIn" |
||
"OnboardRefClk" (PCI) |
||
NIFGEN_VAL_AUTOMATIC (default) |
"None" |
|
"PXI_CLK10" (PXI), "RTSI7" (PCI) |
||
"ClkIn" / "RefIn" |
||
"OnboardRefClk" (PCI) |
||
"ClkIn" |
Not Applicable |
Not Applicable |
"PXI_Star" | ||
"PXI_Trig<0..6>" |
||
| *These column headings refer to NI-FGEN properties and attributes and the values in the columns represent the values that can be set on these properties or attributes. Settings that line up horizontally show valid combinations of the NI-FGEN attribute settings. | ||
Sample Clock Source
The Sample Clock source is the clock from which the Sample clock is derived, and is used to drive the DAC and all waveform generation operations on the device. The default NI-FGEN setting for Sample clock source that drives the Sample clock is Internal. The Sample clock source only needs to be configured during applications that require an external Sample clock.
The NI 5412 supports five options for the Sample clock source: Internal and three External Sources for PXI and two External sources for PCI. The fundamental clock source for your waveform generation application is the Sample clock timebase. The NI 5412 provides a high-precision 100 MHz Voltage Controlled Crystal Oscillator (VCXO) internal source from which all waveform generation operations are derived. The External Sources are the NI 5412 CLK IN front panel connector, PXI_STAR (PXI), PXI_Trig<0..6> (PXI), and the RTSI<0..6> (PCI) lines.
For more information about configuring the Sample clock source for an External sample clock, refer to External Sample Clock Sources.
Clock Mode
The clock mode determines the method of deriving the Sample clock from the Sample clock timebase. The clock mode is only applicable when using an internal Sample clock.
There are three options for setting the clock mode on your NI 5412: Divide-Down Sampling, High-Resolution Sampling, and the Automatic mode. The default NI-FGEN setting for clock mode is Automatic. The Automatic mode setting in NI-FGEN switches between the Divide-Down and the High-Resolution mode depending on the configured Sample clock rate.
For more information about configuring the clock mode, refer to Internal Sample Clock Sources.
PLL Reference Clock Source
The PLL Reference clock source controls the source of the control voltage that tunes the VCXO of the Sample clock timebase for internal clock update sources. The phase-locked loop (PLL) circuit adjusts the Sample clock timebase VCXO to synchronize to a Reference clock.
The frequency stability of the Sample clock timebase matches that of the PLL Reference clock when the two are phase-locked. Phase-locking also synchronizes clocks of multiple devices that are phase locked to the same Reference clock.
There are three PXI options and four PCI options for selecting the PLL Reference Clock source on the NI 5412: Internal, PXI_CLK10 (PXI), RTSI7 (PCI), Onboard Reference Clock (PCI), and CLK IN. The default NI-FGEN setting for Reference Clock Source is Internal.
For more information about the NI 5412 phase-locked loop circuit, refer to PLL Reference Clock Sources.