LabWindows/CVI Trigger Routing
The following tables show which values are supported by National Instruments DMMs.
NIDMM_ATTR_MEAS_COMPLETE_DESTINATION
Destination |
Description |
Device |
NI PXI-407x |
NI PCI-4070 |
NI PXI-4065 |
NI PCI/PCIe/USB-4065 |
NI PXI-4060 |
NI PCI-4060 |
NI PCMCIA-4050 |
NIDMM_VAL_NONE (default) |
No destination specified |
√ |
√ |
√ |
√ |
√ |
√ |
— |
NIDMM_VAL_EXTERNAL |
Pin 6 on the AUX Connector |
√ |
√ |
√ |
√ |
√ |
√ |
— |
NIDMM_VAL_TTL0 |
PXI Trigger Line 0 |
√ |
— |
√ |
— |
√1 |
— |
— |
NIDMM_VAL_TTL1 |
PXI Trigger Line 1 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL2 |
PXI Trigger Line 2 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL3 |
PXI Trigger Line 3 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL4 |
PXI Trigger Line 4 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL5 |
PXI Trigger Line 5 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL6 |
PXI Trigger Line 6 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL7 |
PXI Trigger Line 7 |
√ |
— |
√ |
— |
— |
— |
— |
NIDMM_VAL_LBR_TRIG_0 |
Local Bus Right Trigger Line 0 of PXI/SCXI combination chassis |
√3 |
— |
— |
— |
— |
— |
— |
NIDMM_ATTR_TRIGGER_SOURCE
Source |
Description |
Device |
NI PXI-407x |
NI PCI-4070 |
NI PXI-4065 |
NI PCI/PCIe/USB-4065 |
NI PXI-4060 |
NI PCI-4060 |
NI PCMCIA-4050 |
NIDMM_VAL_IMMEDIATE (default) |
No trigger specified |
√ |
√ |
√ |
√ |
√ |
√ |
— |
NIDMM_VAL_EXTERNAL |
Pin 9 on the AUX Connector |
√ |
√ |
√ |
√ |
√ |
√ |
— |
NIDMM_VAL_SOFTWARE_TRIG |
Configures the DMM to wait until niDMM_SendSoftwareTrigger is called |
√ |
√ |
√ |
√ |
√ |
√ |
— |
NIDMM_VAL_TTL0 |
PXI Trigger Line 0 |
√ |
√2 |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL1 |
PXI Trigger Line 1 |
√ |
√2 |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL2 |
PXI Trigger Line 2 |
√ |
√2 |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL3 |
PXI Trigger Line 3 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL4 |
PXI Trigger Line 4 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL5 |
PXI Trigger Line 5 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL6 |
PXI Trigger Line 6 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL7 |
PXI Trigger Line 7 |
√ |
— |
√ |
— |
— |
— |
— |
NIDMM_VAL_PXI_STAR |
PXI STAR Trigger Line |
√ |
— |
√ |
— |
— |
— |
— |
NIDMM_VAL_LBR_TRIG_1 |
Local Bus Right Trigger Line 1 of PXI/SCXI combination chassis |
√3 |
— |
— |
— |
— |
— |
— |
NIDMM_VAL_AUX_TRIG_1 |
Pin 3 on the AUX Connector |
√ |
— |
√ |
√ |
— |
— |
— |
NIDMM_ATTR_SAMPLE_TRIGGER
Source |
Description |
Device |
NI PXI-407x |
NI PCI-4070 |
NI PXI-4065 |
NI PCI/PCIe/USB-4065 |
NI PXI-4060 |
NI PCI-4060 |
NI PCMCIA-4050 |
NIDMM_VAL_IMMEDIATE (default) |
No trigger specified |
√ |
√ |
√ |
√ |
√ |
√ |
√ |
NIDMM_VAL_EXTERNAL |
Pin 9 on the AUX Connector |
√ |
√ |
√ |
√ |
√ |
√ |
— |
NIDMM_VAL_SOFTWARE |
Configures the DMM to wait until niDMM_SendSoftwareTrigger is called |
√ |
√ |
√ |
√ |
√ |
√ |
— |
NIDMM_VAL_INTERVAL |
Interval Trigger |
√ |
√ |
√ |
√ |
√ |
√ |
√ |
NIDMM_VAL_TTL0 |
PXI Trigger Line 0 |
√ |
√2 |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL1 |
PXI Trigger Line 1 |
√ |
√2 |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL2 |
PXI Trigger Line 2 |
√ |
√2 |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL3 |
PXI Trigger Line 3 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL4 |
PXI Trigger Line 4 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL5 |
PXI Trigger Line 5 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL6 |
PXI Trigger Line 6 |
√ |
— |
√ |
— |
√ |
— |
— |
NIDMM_VAL_TTL7 |
PXI Trigger Line 7 |
√ |
— |
√ |
— |
— |
— |
— |
NIDMM_VAL_PXI_STAR |
PXI STAR Trigger Line |
√ |
— |
√ |
— |
— |
— |
— |
NIDMM_VAL_LBR_TRIG_1 |
Local Bus Right Trigger Line 1 of PXI/SCXI combination chassis |
√3 |
— |
— |
— |
— |
— |
— |
NIDMM_VAL_AUX_TRIG_1 |
Pin 3 on the AUX Connector |
√ |
— |
√ |
√ |
— |
— |
— |
1 Specify TTL0 when the NI PXI-4060 is installed in the right-most slot of a combination chassis to generate MC on Local Bus Right Trigger Line 0 of the SCXI internal trigger lines.
2 Lines TTL0, TTL1, and TTL2 refer to the device interconnect on the NI PCI-4070.
3 Refer to the chassis section for more information regarding limitations of using this feature.