MT Convolutional Interleave VI
Performs the interleaving process using a set of branches that the data elements cyclically pass through.
Each branch has different delays associated with it. Hence the data input of each interleaver branch is delayed by a specific amount (the amount of delay in that particular branch) before the interleaver returns the data. A convolutional interleaver is twice as efficient as a block interleaver.
Use the pull-down menu to select an instance of this VI.
MT Convolutional Interleaver (Standard)
This polymorphic instance performs the interleaving process using a fixed number of branches and a fixed unit delay.
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data in specifies the input data to the interleaver. The default is empty. |
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number of branches specifies the number of branches of the convolutional interleaver. Data elements pass through the branches in a cyclic fashion. For example, in an N branch convolutional interleaver, data element 0 goes through branch 0, element 1 goes through branch 1, element N–1 goes through branch N–1, element N returns through branch 0 and so on. Each branch incorporates different delays. The default is empty. |
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unit delay specifies the unit delay value. If this value is defined as D, then the number of delays on the ith branch is (i×D). If the total number of branches is N, then i=0,1,…, N–1. The default is 1. |
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initial state specifies the shift register values when the convolutional interleaver begins operation. The default is empty. |
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reset? specifies whether to check the current input parameters. On the first call to this VI or when reset? is set to TRUE, the VI checks input parameters. The default is TRUE. |
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error in (no error) can accept error information wired from previously called VIs. Use this information to decide if any functionality should be bypassed in the event of errors from other VIs. Right-click the front panel error in control and select Explain Error or Explain Warning from the shortcut menu for more information about the error.
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data out returns the convolutional interleaved data. |
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error out passes error or warning information out of a VI to be used by other VIs. Right-click the front panel error out indicator and select Explain Error or Explain Warning from the shortcut menu for more information about the error.
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MT Convolutional Interleaver (Generic)
This polymorphic instance performs the interleaving process with user-specified delays for each branch.
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data in specifies the input data to the interleaver. The default is empty. |
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interleaver delays specifies the number of delays individually for each branch of the corresponding interleaver. The number of elements in this array determines the number of branches, and the value of each element denotes the delay for that branch. For example, if interleaver delays is [3,6,9,2], then it implies that branch 0 has 3 delays, branch 1 has 6 delays, and so on, for the corresponding interleaver. The default is empty.
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initial state specifies the shift register values when the convolutional interleaver begins operation. The default is empty. |
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reset? specifies whether to check the current input parameters. On the first call to this VI or when reset? is set to TRUE, the VI checks input parameters. The default is TRUE. |
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error in (no error) can accept error information wired from previously called VIs. Use this information to decide if any functionality should be bypassed in the event of errors from other VIs. Right-click the front panel error in control and select Explain Error or Explain Warning from the shortcut menu for more information about the error.
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data out returns the convolutional interleaved data. |
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error out passes error or warning information out of a VI to be used by other VIs. Right-click the front panel error out indicator and select Explain Error or Explain Warning from the shortcut menu for more information about the error.
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Details
The following example demonstrates convolutional interleaving/deinterleaving.
Let the data in be: x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, …
| Interleaver Input |
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Interleaver Output |
D = unit delay in the path.
Assume for this example that the unit delay = 1, and the initial state shift registers are initialized with values of 0 for both the interleaver and the deinterleaver.
Interleaved Data: x0, 0, 0, 0, x4, x1, 0, 0, x8, x5, x2, 0, x12, x9, ….
| Deinterleaver Input |
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Deinterleaver Output |
Deinterleaved Data: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, …
References
- Wicker, Stephen B. Error Control Systems for Digital Communication and Storage. Englewood Cliffs: Prentice-Hall, 1995.
- Proakis, John G. and Masoud Salehi Communication Systems Engineering. 2d ed. Englewood Cliffs: Prentice-Hall, 2001.
- Sklar, Bernard. Digital Communications: Fundamentals and Applications. 2d ed. Englewood Cliffs: Prentice-Hall, 2001.