There are several features in the TCP/IP stack that use external storage to maintain structures or web pages. Support for a few storage devices is included with the stack; the support files can be used as a template to write drivers for other devices as well. The HardwareProfile.h pin definitions are roughly equivalent for each storage device, except for the first word of the macro, which indicates which type of storage device it applies to (e.g. EEPROM_CS_IO vs SPIFLASH_CS_IO). There are three different storage media.
EEPROM
A EEPROM can be used to store MPFS2 web page images and custom application structures. To indicate to the stack that it should use a EEPROM to store MPFS2 images, define the macro MPFS_USE_EEPROM in the TCPIPConfig.h header file. By default, the stack includes a driver for Microchip’s 25LC256 EEPROM family (to use the 1 Mbit EEPROM, you must also define the macro USE_EEPROM_25LC1024 in TCPIPConfig.h). The macros to control communication with the EEPROM will be prepended with the string EEPROM_ in this case. To enable communication, define EEPROM_CS_TRIS and include the files SPIEEPROM.c and XEEPROM.h in your application. These files may requires some changes to support additional EEPROM devices.
Serial Flash
Storage for MPFS images and custom structures is also available on serial flash devices (tested with SST 25VF016B and Spansion 25FL040A). To indicate that the stack should use serial flash to store web pages, define MPFS_USE_SPI_FLASH in TCPIPConfig.h. The communicaiton macros will be prepended with the string SPIFLASH_ in this case. To enable communication functionality, define SPIFLASH_CS_TRIS and include the files SPIFlash.c and SPIFlash.h in your application. These files may require some changes to support additional flash devices. There are several macros included within “SPIFlash.h” that must also be defined, including macros to define the sector and page sizes, and macros to describe whether the SST or Spansion flash device is being used.
SRAM
A serial RAM can be used to store FIFO blocks and TCP Control Blocks for sockets (tested with AMT Semiconductor’s N256S0830HDA). The macros will be prepended with the string SPIRAM_ in this case. To use this functionality, define EEPROM_CS_TRIS and include the files “SPIRAM.c” and “SPIRAM.h” in your application. These files may require some changes to support additional RAM devices.
|
Macro |
Purpose |
Sample Value |
|
xxxxxx_CS_IO |
Defines the LAT (or PORT, where applicable) register bit that corresponds to the chip select pin. Defining this macro will indicate that the stack should use the specified type of external storage. |
LATDbits.LATD12 |
|
xxxxxx_CS_TRIS |
Defines the TRIS bit that corresponds to the chip select pin on the device. |
TRISDbits.TRISD12 |
|
xxxxxx_SCK_TRIS |
Defines the TRIS bit that corresponds to the clock pin of the SPI module connected to the device. |
TRISGbits.TRISG6 |
|
xxxxxx_SDI_TRIS |
Defines the TRIS bit that corresponds to the data-in pin of the SPI module connected to the device. |
TRISGbits.TRISG7 |
|
xxxxxx_SDO_TRIS |
Defines the TRIS bit that corresponds to the data-out pin of the SPI module connected to the device. |
TRISGbits.TRISG8 |
|
xxxxxx_SPI_IF |
Points to the interrupt flag for the SPI module connected to the device. |
IFS2bits.SPI2IF |
|
xxxxxx_SSPBUF |
Points to the SPI buffer register for the SPI module connected to the device. |
SPI2BUF |
|
xxxxxx_SPICON1 |
Points to the SPI control register for the SPI module connected to the device. |
SPI2CON1 |
|
xxxxxx_SPICON1bits |
Provides bitwise access to the SPI control register for the SPI module connected to the device. The ____bits registers are typically defined in the processor’s header files. |
SPI2CON1bits |
|
xxxxxx_SPICON2 |
Points to the second SPI control register for the SPI module connected to the device. If your device doesn’t have an SPICON2 register (e.g. PIC32) just omit this definition. |
SPI2CON2 |
|
xxxxxx_SPISTAT |
Points to the SPI status register for the SPI module connected to the device. |
SPI2STAT |
|
xxxxxx_SPISTATbits |
Provides bitwise access to the SPI status register for the SPI module connected to the device. |
SPI2STATbits |
|
xxxxxx_SPIBRG |
Points to the SPI Baud Rate Generator register for the SPI module connected to the device. If your device doesn’t have a BRG-based SPI module, just omit this definition. |
SPI2BRG |