To use the ENC624J600 or -424J600 in your project, include “ENCX24J600.c” and “ENCX24J600.h” and uncomment the following macro in HardwareProfile.h:
#define ENC100_INTERFACE_MODE 0The parameter ‘0’ indicates that you’ll be using the device in SPI mode. Potential usable parameters include:
|
Parameter |
Functionality |
|
0 |
SPI mode using CS, SCK, SI, and SO pins |
|
1 |
8-bit demultiplexed PSP Mode 1 with RD and WR pins |
|
2 |
8-bit demultiplexed PSP Mode 2 with R/~W and EN pins |
|
3 |
16-bit demultiplexed PSP Mode 3 with Rd, WRL, and WRH pins |
|
4 |
16-bit demultiplexed PSP Mode 4 with R/~W, B0SEL, and B1SEL pins |
|
5 |
8-bit multiplexed PSP Mode 5 with RD and WR pins |
|
6 |
8-bit multiplexed PSP Mode 6 with R/~W and EN pins |
|
9 |
16-bit multiplexed PSP Mode 9 with AL, RD, WRL, and WRH pins |
|
10 |
16-bit multiplexed PSP Mode 10 with AL, R/~W, B0SEL, and B1SEL pins |
More information on the functionality of each mode is available in the ENC624J600 family datasheet. Note, however, that the 44-pin ENC424J600 only supports communication using the SPI mode and PSP Modes 5 and 6. Also, because of board conflicts, PSP Modes 2, 4, 6, and 10 shouldn’t be used with the Explorer 16 (and PSP Mode 3 may cause bus contention with the 25LC256 EEPROM).
Several macros need to be mapped to registers or register bits when using the ENCX24J600 as well. In addition, some features can be enabled/disabled for this device by defining certain macros. Macros include:
|
Macro |
Purpose |
Sample Value |
|
ENC100_INTERFACE_MODE |
Indicates which communication mode the stack should use to interface to the chip. This macro will also indicate that the stack should use the ENCX24J600. |
0 |
|
ENC100_PSP_USE_INDIRECT_- RAM_ADDRESSING |
Un-commenting this macro will allow the stack to indirectly address the RAM of the ENCX24J600 (to save some address wires). For SPI mode or PSP Modes 9 and 10, this option will be ignored. |
N/A |
|
ENC100_TRANSLATE_TO_PIN- _ADDR(a) |
This macro will actually remap the addresses passed into the parallel interface to fit the configuration of the pins (if you are using indirect addressing). |
((((a)&0x100)<<6) | ((a&0x00FF)) |
|
ENC100_MDIX_IO |
If you design an Auto-crossover (Auto-MDIX) circuit into your board, this macro will define the pin to use for it. See the Fast 100Mbps Ethernet PICtail/PICtail Plus board schematic for an example circuit. |
LATBbits.LATB3 |
|
ENC100_MDIX_TRIS |
Defines the TRIS bit to use for the Auto-crossover circuit. |
TRISBbits.TRISB3 |
|
ENC100_INT_IO |
Defines an I/O pin to use for the chip’s interrupt signal pin. This feature is currently unused by the stack. |
PORTAbits.RA13 |
|
ENC100_INT_TRIS |
Defines a TRIS bit to use for the chip’s interrupt signal pin. |
TRISAbits.TRISA13 |
|
ENC100_CS_IO |
Defines a port bit for use with the chip select pin. Optional in PSP modes. |
LATAbits.LATA5 |
|
ENC100_CS_TRIS |
Defines a TRIS bit to use for the chip select pin. |
TRISAbits.TRISA5 |
|
ENC100_POR_IO |
Defines the port bit to use with a power disconnect circuit. If your application doesn’t have this feature implemented, comment out this bit. |
LATCbits.LATC1 |
|
ENC100_POR_TRIS |
Defines the TRIS bit to use with a power disconnect circuit. |
TRISCbits.TRISC1 |
|
ENC100_SO_WR_B0SEL_EN_IO |
Defines a pin used for communication. The functionality of this pin depends on which communication mode in selected. It can be equivalent to the ENCX24J600 serial out pin, the parallel mode WR strobe, the B0SEL pin, or the EN pin. |
LATDbits.LATD4 |
|
ENC100_SO_WR_B0SEL_EN_TRIS |
Defines the TRIS bit to use with the ENC100_SO_WR_B0SEL_EN_IO pin. |
TRISDbits.TRISD4 |
|
ENC100_SI_RD_RW_IO |
Defines a pin used for communication. The functionality of this pin depends on which communication mode in selected. It can be equivalent to the ENCX24J600 serial in pin, the parallel mode RD strobe, or the R/~W pin. |
LATDbits.LATD5 |
|
ENC100_SI_RD_RW_TRIS |
Defines the TRIS bit to use with the ENC100_SI_RD_RW_IO pin. |
TRISDbits.TRISD5 |
|
ENC100_SCK_AL_IO |
Defines a pin used for communication. The functionality of this pin depends on which communication mode in selected. It can be equivalent to the ENCX24J600 serial clock pin or the parallel mode address latch strobe. |
LATDbits.LATDB15 |
|
ENC100_SCK_AL_TRIS |
Defines the TRIS bit to use with the ENC100_SCK_AL_IO pin. |
TRISDbits.TRISD15 |
|
ENC100_ISR_ENABLE |
Points to the bit to enable the interrupt for the I/O based ENCX24J600-triggered interrupt. This feature is not currently implemented. |
IEC1bits.INT2IE |
|
ENC100_ISR_FLAG |
Points to the interrupt flag bit for the I/O based ENCX24J600-triggered interrupt. This feature is not currently implemented. |
IFS1bits.INT2IF |
|
ENC100_ISR_POLARITY |
Points to the interrupt polarity bit for the I/O based ENCX24J600-triggered interrupt. This feature is not currently implemented. |
INTCON2bits.INT2EP |
|
ENC100_ISR_PRIORITY |
Points to the interrupt priority bit for the I/O based ENCX24J600-triggered interrupt. This feature is not currently implemented. |
IPC7bits.INT2IP |
|
ENC100_SPI_ENABLE |
Points to the SPI module enable bit if SPI mode is used. |
SPI1STATbits.SPIEN |
|
ENC100_SPI_IF |
Points to the interrupt flag for the SPI module if SPI mode is used. |
IFS0bits.SPI1IF |
|
ENC100_SSPBUF |
Points to the SPI buffer register for the SPI module if SPI mode is used. |
SPI1BUF |
|
ENC100_SPISTAT |
Points to the SPI status register for the SPI module if SPI mode is used. |
SPI1STAT |
|
ENC100_SPISTATbits |
Provides bitwise access to the SPI status register for the SPI if SPI mode is used. The ____bits registers are typically defined in the processor’s header files. |
SPI1STATbits |
|
ENC100_SPICON1 |
Points to the SPI control register for the SPI module if SPI mode is used. |
SPI1CON1 |
|
ENC100_SPICON1bits |
Provides bitwise access to the SPI control register for the SPI module if SPI mode is used (see ENC_SPISTATbits entry). |
SPI1CON1bits |
|
ENC100_SPICON2 |
Points to the second SPI control register for the SPI module if SPI mode is used. If your device doesn’t have an SPICON2 register (e.g. PIC32) just omit this definition. |
SPI1CON2 |
|
ENC100_SPIBRG |
Points to the SPI Baud Rate Generator register for the SPI module if SPI mode is used. If your device doesn’t have a BRG-based SPI module, just omit this definition. |
SPI1BRG |