FIFO Buffers

FIFO buffers are present on the 16550-compatible UARTs—one for the transmitter and one for the receiver. The Receive Buffer control sets the number of characters received in the FIFO before the PC is interrupted to read the data. The Transmit Buffer control sets the maximum number of bytes written to the FIFO in a block when the PC is interrupted to write the data.

The built-in ports on PXI RT controllers and the PCI, PXI, and PCMCIA plug-in serial boards have configurable FIFO settings. Use the Advanced tab in MAX to configure your FIFO settings. When you configure FIFO settings, consider the following points:

• You can select larger FIFO buffer sizes to reduce the number of interrupts your PC receives and thereby minimize system overhead.
• If transfer rates are high, you can lower the Receive Buffer value to prevent overrun errors due to interrupt latency.
• If your data transfer sizes are small, and your Receive Buffer value is above your data sizes, your system is less efficient. For maximum efficiency, set your Receive Buffer value such that your data transfer size is a multiple of that value.