C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_i2c.h
Go to the documentation of this file.00001 /***********************************************************************/ 00021 /* Peripheral group ----------------------------------------------------------- */ 00027 #ifndef LPC17XX_I2C_H_ 00028 #define LPC17XX_I2C_H_ 00029 00030 /* Includes ------------------------------------------------------------------- */ 00031 #include "LPC17xx.h" 00032 #include "lpc_types.h" 00033 00034 00035 #ifdef __cplusplus 00036 extern "C" 00037 { 00038 #endif 00039 00040 00041 /* Private Macros ------------------------------------------------------------- */ 00050 /*******************************************************************/ 00053 #define I2C_I2CONSET_AA ((0x04)) 00054 #define I2C_I2CONSET_SI ((0x08)) 00055 #define I2C_I2CONSET_STO ((0x10)) 00056 #define I2C_I2CONSET_STA ((0x20)) 00057 #define I2C_I2CONSET_I2EN ((0x40)) 00060 /*******************************************************************/ 00064 #define I2C_I2CONCLR_AAC ((1<<2)) 00065 00066 #define I2C_I2CONCLR_SIC ((1<<3)) 00067 00068 #define I2C_I2CONCLR_STAC ((1<<5)) 00069 00070 #define I2C_I2CONCLR_I2ENC ((1<<6)) 00071 00072 00073 /********************************************************************/ 00076 /* Return Code in I2C status register */ 00077 #define I2C_STAT_CODE_BITMASK ((0xF8)) 00078 00079 /* I2C return status code definitions ----------------------------- */ 00080 00082 #define I2C_I2STAT_NO_INF ((0xF8)) 00083 00084 /* Master transmit mode -------------------------------------------- */ 00086 #define I2C_I2STAT_M_TX_START ((0x08)) 00087 00088 #define I2C_I2STAT_M_TX_RESTART ((0x10)) 00089 00090 #define I2C_I2STAT_M_TX_SLAW_ACK ((0x18)) 00091 00092 #define I2C_I2STAT_M_TX_SLAW_NACK ((0x20)) 00093 00094 #define I2C_I2STAT_M_TX_DAT_ACK ((0x28)) 00095 00096 #define I2C_I2STAT_M_TX_DAT_NACK ((0x30)) 00097 00098 #define I2C_I2STAT_M_TX_ARB_LOST ((0x38)) 00099 00100 /* Master receive mode -------------------------------------------- */ 00102 #define I2C_I2STAT_M_RX_START ((0x08)) 00103 00104 #define I2C_I2STAT_M_RX_RESTART ((0x10)) 00105 00106 #define I2C_I2STAT_M_RX_ARB_LOST ((0x38)) 00107 00108 #define I2C_I2STAT_M_RX_SLAR_ACK ((0x40)) 00109 00110 #define I2C_I2STAT_M_RX_SLAR_NACK ((0x48)) 00111 00112 #define I2C_I2STAT_M_RX_DAT_ACK ((0x50)) 00113 00114 #define I2C_I2STAT_M_RX_DAT_NACK ((0x58)) 00115 00116 /* Slave receive mode -------------------------------------------- */ 00118 #define I2C_I2STAT_S_RX_SLAW_ACK ((0x60)) 00119 00121 #define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68)) 00122 00123 //#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68)) 00124 00126 #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70)) 00127 00129 #define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78)) 00130 00131 //#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78)) 00132 00135 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80)) 00136 00138 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88)) 00139 00141 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90)) 00142 00144 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98)) 00145 00148 #define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0)) 00149 00152 #define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8)) 00153 00155 #define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0)) 00156 00157 //#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0)) 00158 00160 #define I2C_I2STAT_S_TX_DAT_ACK ((0xB8)) 00161 00162 #define I2C_I2STAT_S_TX_DAT_NACK ((0xC0)) 00163 00165 #define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8)) 00166 00168 #define I2C_SLAVE_TIME_OUT 0x10000UL 00169 00170 /********************************************************************/ 00174 #define I2C_I2DAT_BITMASK ((0xFF)) 00175 00179 #define I2C_I2DAT_IDLE_CHAR (0xFF) 00180 00181 00182 /********************************************************************/ 00185 #define I2C_I2MMCTRL_MM_ENA ((1<<0)) 00186 #define I2C_I2MMCTRL_ENA_SCL ((1<<1)) 00187 #define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) 00188 #define I2C_I2MMCTRL_BITMASK ((0x07)) 00191 /********************************************************************/ 00195 #define I2DATA_BUFFER_BITMASK ((0xFF)) 00196 00197 00198 /********************************************************************/ 00202 #define I2C_I2ADR_GC ((1<<0)) 00203 00204 #define I2C_I2ADR_BITMASK ((0xFF)) 00205 00206 00207 /********************************************************************/ 00211 #define I2C_I2MASK_MASK(n) ((n&0xFE)) 00212 00213 00214 /********************************************************************/ 00218 #define I2C_I2SCLH_BITMASK ((0xFFFF)) 00219 00220 00221 /********************************************************************/ 00225 #define I2C_I2SCLL_BITMASK ((0xFFFF)) 00226 00237 /* Public Types --------------------------------------------------------------- */ 00243 typedef struct { 00244 uint8_t SlaveAddrChannel; 00247 uint8_t SlaveAddr_7bit; 00248 uint8_t GeneralCallState; 00253 uint8_t SlaveAddrMaskValue; 00261 } I2C_OWNSLAVEADDR_CFG_Type; 00262 00263 00265 typedef struct 00266 { 00267 uint32_t sl_addr7bit; 00268 uint8_t* tx_data; 00270 uint32_t tx_length; 00272 uint32_t tx_count; 00273 uint8_t* rx_data; 00275 uint32_t rx_length; 00277 uint32_t rx_count; 00278 uint32_t retransmissions_max; 00279 uint32_t retransmissions_count; 00280 uint32_t status; 00281 void (*callback)(void); 00283 } I2C_M_SETUP_Type; 00284 00285 00287 typedef struct 00288 { 00289 uint8_t* tx_data; 00290 uint32_t tx_length; 00291 uint32_t tx_count; 00292 uint8_t* rx_data; 00293 uint32_t rx_length; 00294 uint32_t rx_count; 00295 uint32_t status; 00296 void (*callback)(void); 00297 } I2C_S_SETUP_Type; 00298 00302 typedef enum { 00303 I2C_TRANSFER_POLLING = 0, 00304 I2C_TRANSFER_INTERRUPT 00305 } I2C_TRANSFER_OPT_Type; 00306 00307 00313 /* Public Macros -------------------------------------------------------------- */ 00318 #define PARAM_I2C_SLAVEADDR_CH(n) ((n>=0) && (n<=3)) 00319 00321 #define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \ 00322 || (((uint32_t *)n)==((uint32_t *)LPC_I2C1)) \ 00323 || (((uint32_t *)n)==((uint32_t *)LPC_I2C2))) 00324 00325 /* I2C status values */ 00326 #define I2C_SETUP_STATUS_ARBF (1<<8) 00327 #define I2C_SETUP_STATUS_NOACKF (1<<9) 00328 #define I2C_SETUP_STATUS_DONE (1<<10) 00331 /*********************************************************************/ 00334 #define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL 00335 #define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL 00337 #define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL)) 00338 00344 /* Public Functions ----------------------------------------------------------- */ 00349 void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock); 00350 void I2C_DeInit(LPC_I2C_TypeDef* I2Cx); 00351 void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate); 00352 void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, FunctionalState NewState); 00353 00354 Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \ 00355 I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); 00356 Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \ 00357 I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); 00358 00359 void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct); 00360 uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx); 00361 00362 void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState); 00363 void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState); 00364 uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx); 00365 00366 void I2C0_StdIntHandler(void); 00367 void I2C1_StdIntHandler(void); 00368 void I2C2_StdIntHandler(void); 00369 00370 00376 #ifdef __cplusplus 00377 } 00378 #endif 00379 00380 #endif /* LPC17XX_I2C_H_ */ 00381 00386 /* --------------------------------- End Of File ------------------------------ */
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