SSP_Public_Macros
[SSP]
Defines | |
| #define | PARAM_SSPx(n) |
| #define | SSP_CPHA_FIRST ((uint32_t)(0)) |
| #define | SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND |
| #define | PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND)) |
| #define | SSP_CPOL_HI ((uint32_t)(0)) |
| #define | SSP_CPOL_LO SSP_CR0_CPOL_HI |
| #define | PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO)) |
| #define | SSP_SLAVE_MODE SSP_CR1_SLAVE_EN |
| #define | SSP_MASTER_MODE ((uint32_t)(0)) |
| #define | PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE)) |
| #define | SSP_DATABIT_4 SSP_CR0_DSS(4) |
| #define | SSP_DATABIT_5 SSP_CR0_DSS(5) |
| #define | SSP_DATABIT_6 SSP_CR0_DSS(6) |
| #define | SSP_DATABIT_7 SSP_CR0_DSS(7) |
| #define | SSP_DATABIT_8 SSP_CR0_DSS(8) |
| #define | SSP_DATABIT_9 SSP_CR0_DSS(9) |
| #define | SSP_DATABIT_10 SSP_CR0_DSS(10) |
| #define | SSP_DATABIT_11 SSP_CR0_DSS(11) |
| #define | SSP_DATABIT_12 SSP_CR0_DSS(12) |
| #define | SSP_DATABIT_13 SSP_CR0_DSS(13) |
| #define | SSP_DATABIT_14 SSP_CR0_DSS(14) |
| #define | SSP_DATABIT_15 SSP_CR0_DSS(15) |
| #define | SSP_DATABIT_16 SSP_CR0_DSS(16) |
| #define | PARAM_SSP_DATABIT(n) |
| #define | SSP_FRAME_SPI SSP_CR0_FRF_SPI |
| #define | SSP_FRAME_TI SSP_CR0_FRF_TI |
| #define | SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE |
| #define | PARAM_SSP_FRAME(n) |
| #define | SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE |
| #define | SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF |
| #define | SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE |
| #define | SSP_STAT_RXFIFO_FULL SSP_SR_RFF |
| #define | SSP_STAT_BUSY SSP_SR_BSY |
| #define | PARAM_SSP_STAT(n) |
| #define | SSP_INTCFG_ROR SSP_IMSC_ROR |
| #define | SSP_INTCFG_RT SSP_IMSC_RT |
| #define | SSP_INTCFG_RX SSP_IMSC_RX |
| #define | SSP_INTCFG_TX SSP_IMSC_TX |
| #define | PARAM_SSP_INTCFG(n) |
| #define | SSP_INTSTAT_ROR SSP_MIS_ROR |
| #define | SSP_INTSTAT_RT SSP_MIS_RT |
| #define | SSP_INTSTAT_RX SSP_MIS_RX |
| #define | SSP_INTSTAT_TX SSP_MIS_TX |
| #define | PARAM_SSP_INTSTAT(n) |
| #define | SSP_INTSTAT_RAW_ROR SSP_RIS_ROR |
| #define | SSP_INTSTAT_RAW_RT SSP_RIS_RT |
| #define | SSP_INTSTAT_RAW_RX SSP_RIS_RX |
| #define | SSP_INTSTAT_RAW_TX SSP_RIS_TX |
| #define | PARAM_SSP_INTSTAT_RAW(n) |
| #define | SSP_INTCLR_ROR SSP_ICR_ROR |
| #define | SSP_INTCLR_RT SSP_ICR_RT |
| #define | PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT)) |
| #define | SSP_DMA_TX SSP_DMA_RXDMA_EN |
| #define | SSP_DMA_RX SSP_DMA_TXDMA_EN |
| #define | PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX)) |
| #define | SSP_STAT_DONE (1UL<<8) |
| #define | SSP_STAT_ERROR (1UL<<9) |
Define Documentation
| #define PARAM_SSP_CPHA | ( | n | ) | ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND)) |
Definition at line 267 of file lpc17xx_ssp.h.
| #define PARAM_SSP_CPOL | ( | n | ) | ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO)) |
Definition at line 278 of file lpc17xx_ssp.h.
| #define PARAM_SSP_DATABIT | ( | n | ) |
Value:
((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \ || (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \ || (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \ || (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \ || (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \ || (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \ || (n==SSP_DATABIT_15))
Definition at line 299 of file lpc17xx_ssp.h.
| #define PARAM_SSP_DMA | ( | n | ) | ((n==SSP_DMA_TX) || (n==SSP_DMA_RX)) |
Definition at line 407 of file lpc17xx_ssp.h.
| #define PARAM_SSP_FRAME | ( | n | ) |
Value:
((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\ || (n==SSP_FRAME_MICROWIRE))
Definition at line 315 of file lpc17xx_ssp.h.
| #define PARAM_SSP_INTCFG | ( | n | ) |
Value:
((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \ || (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
Definition at line 350 of file lpc17xx_ssp.h.
| #define PARAM_SSP_INTCLR | ( | n | ) | ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT)) |
Definition at line 396 of file lpc17xx_ssp.h.
| #define PARAM_SSP_INTSTAT | ( | n | ) |
Value:
((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \ || (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
Definition at line 366 of file lpc17xx_ssp.h.
| #define PARAM_SSP_INTSTAT_RAW | ( | n | ) |
Value:
((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \ || (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
Definition at line 382 of file lpc17xx_ssp.h.
| #define PARAM_SSP_MODE | ( | n | ) | ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE)) |
Definition at line 283 of file lpc17xx_ssp.h.
| #define PARAM_SSP_STAT | ( | n | ) |
Value:
((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \ || (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \ || (n==SSP_STAT_BUSY))
Definition at line 333 of file lpc17xx_ssp.h.
| #define PARAM_SSPx | ( | n | ) |
Value:
Macro to determine if it is valid SSP port numberDefinition at line 258 of file lpc17xx_ssp.h.
| #define SSP_CPHA_FIRST ((uint32_t)(0)) |
SSP configuration parameter defines Clock phase control bit
Definition at line 265 of file lpc17xx_ssp.h.
| #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND |
Definition at line 266 of file lpc17xx_ssp.h.
| #define SSP_CPOL_HI ((uint32_t)(0)) |
Clock polarity control bit
Definition at line 276 of file lpc17xx_ssp.h.
| #define SSP_CPOL_LO SSP_CR0_CPOL_HI |
Definition at line 277 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_10 SSP_CR0_DSS(10) |
Databit number = 10
Definition at line 292 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_11 SSP_CR0_DSS(11) |
Databit number = 11
Definition at line 293 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_12 SSP_CR0_DSS(12) |
Databit number = 12
Definition at line 294 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_13 SSP_CR0_DSS(13) |
Databit number = 13
Definition at line 295 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_14 SSP_CR0_DSS(14) |
Databit number = 14
Definition at line 296 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_15 SSP_CR0_DSS(15) |
Databit number = 15
Definition at line 297 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_16 SSP_CR0_DSS(16) |
Databit number = 16
Definition at line 298 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_4 SSP_CR0_DSS(4) |
SSP data bit number defines Databit number = 4
Definition at line 286 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_5 SSP_CR0_DSS(5) |
Databit number = 5
Definition at line 287 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_6 SSP_CR0_DSS(6) |
Databit number = 6
Definition at line 288 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_7 SSP_CR0_DSS(7) |
Databit number = 7
Definition at line 289 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_8 SSP_CR0_DSS(8) |
Databit number = 8
Definition at line 290 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_9 SSP_CR0_DSS(9) |
Databit number = 9
Definition at line 291 of file lpc17xx_ssp.h.
| #define SSP_DMA_RX SSP_DMA_TXDMA_EN |
SSP bit for enabling TX DMA
Definition at line 405 of file lpc17xx_ssp.h.
| #define SSP_DMA_TX SSP_DMA_RXDMA_EN |
SSP DMA defines SSP bit for enabling RX DMA
Definition at line 403 of file lpc17xx_ssp.h.
| #define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE |
National Micro-wire mode
Definition at line 313 of file lpc17xx_ssp.h.
| #define SSP_FRAME_SPI SSP_CR0_FRF_SPI |
SSP Frame Format definition Motorola SPI mode
Definition at line 309 of file lpc17xx_ssp.h.
| #define SSP_FRAME_TI SSP_CR0_FRF_TI |
TI synchronous serial mode
Definition at line 311 of file lpc17xx_ssp.h.
| #define SSP_INTCFG_ROR SSP_IMSC_ROR |
SSP Interrupt Configuration defines Receive Overrun
Definition at line 342 of file lpc17xx_ssp.h.
| #define SSP_INTCFG_RT SSP_IMSC_RT |
Receive TimeOut
Definition at line 344 of file lpc17xx_ssp.h.
| #define SSP_INTCFG_RX SSP_IMSC_RX |
Rx FIFO is at least half full
Definition at line 346 of file lpc17xx_ssp.h.
| #define SSP_INTCFG_TX SSP_IMSC_TX |
Tx FIFO is at least half empty
Definition at line 348 of file lpc17xx_ssp.h.
| #define SSP_INTCLR_ROR SSP_ICR_ROR |
SSP Interrupt Clear defines Writing a 1 to this bit clears the "frame was received when RxFIFO was full" interrupt
Definition at line 391 of file lpc17xx_ssp.h.
| #define SSP_INTCLR_RT SSP_ICR_RT |
Writing a 1 to this bit clears the "Rx FIFO was not empty and has not been read for a timeout period" interrupt
Definition at line 394 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR |
SSP Raw Interrupt Status defines Receive Overrun
Definition at line 374 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RAW_RT SSP_RIS_RT |
Receive TimeOut
Definition at line 376 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RAW_RX SSP_RIS_RX |
Rx FIFO is at least half full
Definition at line 378 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RAW_TX SSP_RIS_TX |
Tx FIFO is at least half empty
Definition at line 380 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_ROR SSP_MIS_ROR |
SSP Configured Interrupt Status defines Receive Overrun
Definition at line 358 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RT SSP_MIS_RT |
Receive TimeOut
Definition at line 360 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RX SSP_MIS_RX |
Rx FIFO is at least half full
Definition at line 362 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_TX SSP_MIS_TX |
Tx FIFO is at least half empty
Definition at line 364 of file lpc17xx_ssp.h.
| #define SSP_MASTER_MODE ((uint32_t)(0)) |
Definition at line 282 of file lpc17xx_ssp.h.
| #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN |
SSP master mode enable
Definition at line 281 of file lpc17xx_ssp.h.
| #define SSP_STAT_BUSY SSP_SR_BSY |
SSP status SSP Busy bit
Definition at line 331 of file lpc17xx_ssp.h.
| #define SSP_STAT_DONE (1UL<<8) |
Done
Definition at line 410 of file lpc17xx_ssp.h.
| #define SSP_STAT_ERROR (1UL<<9) |
Error
Definition at line 411 of file lpc17xx_ssp.h.
| #define SSP_STAT_RXFIFO_FULL SSP_SR_RFF |
SSP status RX FIFO full bit
Definition at line 329 of file lpc17xx_ssp.h.
| #define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE |
SSP status RX FIFO not empty bit
Definition at line 327 of file lpc17xx_ssp.h.
| #define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE |
SSP Status defines SSP status TX FIFO Empty bit
Definition at line 323 of file lpc17xx_ssp.h.
| #define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF |
SSP status TX FIFO not full bit
Definition at line 325 of file lpc17xx_ssp.h.
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