SSP_REGISTER_BIT_DEFINITION
[SSP_Private_Macros]
Defines | |
#define | SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF)) |
#define | SSP_CR0_FRF_SPI ((uint32_t)(0<<4)) |
#define | SSP_CR0_FRF_TI ((uint32_t)(1<<4)) |
#define | SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4)) |
#define | SSP_CR0_CPOL_HI ((uint32_t)(1<<6)) |
#define | SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7)) |
#define | SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8)) |
#define | SSP_CR0_BITMASK ((uint32_t)(0xFFFF)) |
#define | SSP_CR1_LBM_EN ((uint32_t)(1<<0)) |
#define | SSP_CR1_SSP_EN ((uint32_t)(1<<1)) |
#define | SSP_CR1_SLAVE_EN ((uint32_t)(1<<2)) |
#define | SSP_CR1_SO_DISABLE ((uint32_t)(1<<3)) |
#define | SSP_CR1_BITMASK ((uint32_t)(0x0F)) |
#define | SSP_DR_BITMASK(n) ((n)&0xFFFF) |
#define | SSP_SR_TFE ((uint32_t)(1<<0)) |
#define | SSP_SR_TNF ((uint32_t)(1<<1)) |
#define | SSP_SR_RNE ((uint32_t)(1<<2)) |
#define | SSP_SR_RFF ((uint32_t)(1<<3)) |
#define | SSP_SR_BSY ((uint32_t)(1<<4)) |
#define | SSP_SR_BITMASK ((uint32_t)(0x1F)) |
#define | SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF)) |
#define | SSP_CPSR_BITMASK ((uint32_t)(0xFF)) |
#define | SSP_IMSC_ROR ((uint32_t)(1<<0)) |
#define | SSP_IMSC_RT ((uint32_t)(1<<1)) |
#define | SSP_IMSC_RX ((uint32_t)(1<<2)) |
#define | SSP_IMSC_TX ((uint32_t)(1<<3)) |
#define | SSP_IMSC_BITMASK ((uint32_t)(0x0F)) |
#define | SSP_RIS_ROR ((uint32_t)(1<<0)) |
#define | SSP_RIS_RT ((uint32_t)(1<<1)) |
#define | SSP_RIS_RX ((uint32_t)(1<<2)) |
#define | SSP_RIS_TX ((uint32_t)(1<<3)) |
#define | SSP_RIS_BITMASK ((uint32_t)(0x0F)) |
#define | SSP_MIS_ROR ((uint32_t)(1<<0)) |
#define | SSP_MIS_RT ((uint32_t)(1<<1)) |
#define | SSP_MIS_RX ((uint32_t)(1<<2)) |
#define | SSP_MIS_TX ((uint32_t)(1<<3)) |
#define | SSP_MIS_BITMASK ((uint32_t)(0x0F)) |
#define | SSP_ICR_ROR ((uint32_t)(1<<0)) |
#define | SSP_ICR_RT ((uint32_t)(1<<1)) |
#define | SSP_ICR_BITMASK ((uint32_t)(0x03)) |
#define | SSP_DMA_RXDMA_EN ((uint32_t)(1<<0)) |
#define | SSP_DMA_TXDMA_EN ((uint32_t)(1<<1)) |
#define | SSP_DMA_BITMASK ((uint32_t)(0x03)) |
Detailed Description
Macro defines for CR0 registerDefine Documentation
#define SSP_CPSR_BITMASK ((uint32_t)(0xFF)) |
SSP CPSR bit mask
Definition at line 120 of file lpc17xx_ssp.h.
#define SSP_CPSR_CPDVSR | ( | n | ) | ((uint32_t)(n&0xFF)) |
Macro defines for CPSR register SSP clock prescaler
Definition at line 118 of file lpc17xx_ssp.h.
#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF)) |
SSP CR0 bit mask
Definition at line 72 of file lpc17xx_ssp.h.
#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7)) |
SPI clock out phase bit (used in SPI mode only), (1) = captures data on the second clock transition of the frame, (0) = first
Definition at line 67 of file lpc17xx_ssp.h.
#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6)) |
SPI clock polarity bit (used in SPI mode only), (1) = maintains the bus clock high between frames, (0) = low
Definition at line 64 of file lpc17xx_ssp.h.
#define SSP_CR0_DSS | ( | n | ) | ((uint32_t)((n-1)&0xF)) |
SSP data size select, must be 4 bits to 16 bits
Definition at line 55 of file lpc17xx_ssp.h.
#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4)) |
SSP control 0 National Micro-wire mode
Definition at line 61 of file lpc17xx_ssp.h.
#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4)) |
SSP control 0 Motorola SPI mode
Definition at line 57 of file lpc17xx_ssp.h.
#define SSP_CR0_FRF_TI ((uint32_t)(1<<4)) |
SSP control 0 TI synchronous serial mode
Definition at line 59 of file lpc17xx_ssp.h.
#define SSP_CR0_SCR | ( | n | ) | ((uint32_t)((n&0xFF)<<8)) |
SSP serial clock rate value load macro, divider rate is PERIPH_CLK / (cpsr * (SCR + 1))
Definition at line 70 of file lpc17xx_ssp.h.
#define SSP_CR1_BITMASK ((uint32_t)(0x0F)) |
SSP CR1 bit mask
Definition at line 88 of file lpc17xx_ssp.h.
#define SSP_CR1_LBM_EN ((uint32_t)(1<<0)) |
Macro defines for CR1 register SSP control 1 loopback mode enable bit
Definition at line 79 of file lpc17xx_ssp.h.
#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2)) |
SSP control 1 slave enable
Definition at line 83 of file lpc17xx_ssp.h.
#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3)) |
SSP control 1 slave out disable bit, disables transmit line in slave mode
Definition at line 86 of file lpc17xx_ssp.h.
#define SSP_CR1_SSP_EN ((uint32_t)(1<<1)) |
SSP control 1 enable bit
Definition at line 81 of file lpc17xx_ssp.h.
#define SSP_DMA_BITMASK ((uint32_t)(0x03)) |
DMACR bit mask
Definition at line 188 of file lpc17xx_ssp.h.
#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0)) |
Macro defines for DMACR register SSP bit for enabling RX DMA
Definition at line 184 of file lpc17xx_ssp.h.
#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1)) |
SSP bit for enabling TX DMA
Definition at line 186 of file lpc17xx_ssp.h.
#define SSP_DR_BITMASK | ( | n | ) | ((n)&0xFFFF) |
Macro defines for DR register SSP data bit mask
Definition at line 95 of file lpc17xx_ssp.h.
#define SSP_ICR_BITMASK ((uint32_t)(0x03)) |
ICR bit mask
Definition at line 177 of file lpc17xx_ssp.h.
#define SSP_ICR_ROR ((uint32_t)(1<<0)) |
Macro define for (ICR) Interrupt Clear registers Writing a 1 to this bit clears the "frame was received when RxFIFO was full" interrupt
Definition at line 172 of file lpc17xx_ssp.h.
#define SSP_ICR_RT ((uint32_t)(1<<1)) |
Writing a 1 to this bit clears the "Rx FIFO was not empty and has not been read for a timeout period" interrupt
Definition at line 175 of file lpc17xx_ssp.h.
#define SSP_IMSC_BITMASK ((uint32_t)(0x0F)) |
IMSC bit mask
Definition at line 135 of file lpc17xx_ssp.h.
#define SSP_IMSC_ROR ((uint32_t)(1<<0)) |
Macro define for (IMSC) Interrupt Mask Set/Clear registers Receive Overrun
Definition at line 127 of file lpc17xx_ssp.h.
#define SSP_IMSC_RT ((uint32_t)(1<<1)) |
Receive TimeOut
Definition at line 129 of file lpc17xx_ssp.h.
#define SSP_IMSC_RX ((uint32_t)(1<<2)) |
Rx FIFO is at least half full
Definition at line 131 of file lpc17xx_ssp.h.
#define SSP_IMSC_TX ((uint32_t)(1<<3)) |
Tx FIFO is at least half empty
Definition at line 133 of file lpc17xx_ssp.h.
#define SSP_MIS_BITMASK ((uint32_t)(0x0F)) |
MIS bit mask
Definition at line 164 of file lpc17xx_ssp.h.
#define SSP_MIS_ROR ((uint32_t)(1<<0)) |
Macro define for (MIS) Masked Interrupt Status registers Receive Overrun
Definition at line 156 of file lpc17xx_ssp.h.
#define SSP_MIS_RT ((uint32_t)(1<<1)) |
Receive TimeOut
Definition at line 158 of file lpc17xx_ssp.h.
#define SSP_MIS_RX ((uint32_t)(1<<2)) |
Rx FIFO is at least half full
Definition at line 160 of file lpc17xx_ssp.h.
#define SSP_MIS_TX ((uint32_t)(1<<3)) |
Tx FIFO is at least half empty
Definition at line 162 of file lpc17xx_ssp.h.
#define SSP_RIS_BITMASK ((uint32_t)(0x0F)) |
RIS bit mask
Definition at line 149 of file lpc17xx_ssp.h.
#define SSP_RIS_ROR ((uint32_t)(1<<0)) |
Macro define for (RIS) Raw Interrupt Status registers Receive Overrun
Definition at line 141 of file lpc17xx_ssp.h.
#define SSP_RIS_RT ((uint32_t)(1<<1)) |
Receive TimeOut
Definition at line 143 of file lpc17xx_ssp.h.
#define SSP_RIS_RX ((uint32_t)(1<<2)) |
Rx FIFO is at least half full
Definition at line 145 of file lpc17xx_ssp.h.
#define SSP_RIS_TX ((uint32_t)(1<<3)) |
Tx FIFO is at least half empty
Definition at line 147 of file lpc17xx_ssp.h.
#define SSP_SR_BITMASK ((uint32_t)(0x1F)) |
SSP SR bit mask
Definition at line 111 of file lpc17xx_ssp.h.
#define SSP_SR_BSY ((uint32_t)(1<<4)) |
SSP status SSP Busy bit
Definition at line 109 of file lpc17xx_ssp.h.
#define SSP_SR_RFF ((uint32_t)(1<<3)) |
SSP status RX FIFO full bit
Definition at line 107 of file lpc17xx_ssp.h.
#define SSP_SR_RNE ((uint32_t)(1<<2)) |
SSP status RX FIFO not empty bit
Definition at line 105 of file lpc17xx_ssp.h.
#define SSP_SR_TFE ((uint32_t)(1<<0)) |
Macro defines for SR register SSP status TX FIFO Empty bit
Definition at line 101 of file lpc17xx_ssp.h.
#define SSP_SR_TNF ((uint32_t)(1<<1)) |
SSP status TX FIFO not full bit
Definition at line 103 of file lpc17xx_ssp.h.
Generated on Mon Feb 8 10:01:47 2010 for LPC1700CMSIS Standard Peripheral Firmware Library by 1.5.9