I2S_REGISTER_BIT_DEFINITION
[I2S_Private_Macros]
Defines | |
| #define | I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) |
| #define | I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) |
| #define | I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) |
| #define | I2S_DAO_MONO ((uint32_t)(1<<2)) |
| #define | I2S_DAO_STOP ((uint32_t)(1<<3)) |
| #define | I2S_DAO_RESET ((uint32_t)(1<<4)) |
| #define | I2S_DAO_SLAVE ((uint32_t)(1<<5)) |
| #define | I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6)) |
| #define | I2S_DAO_MUTE ((uint32_t)(1<<15)) |
| #define | I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) |
| #define | I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) |
| #define | I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) |
| #define | I2S_DAI_MONO ((uint32_t)(1<<2)) |
| #define | I2S_DAI_STOP ((uint32_t)(1<<3)) |
| #define | I2S_DAI_RESET ((uint32_t)(1<<4)) |
| #define | I2S_DAI_SLAVE ((uint32_t)(1<<5)) |
| #define | I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6)) |
| #define | I2S_DAI_MUTE ((uint32_t)(1<<15)) |
| #define | I2S_STATE_IRQ ((uint32_t)(1)) |
| #define | I2S_STATE_DMA1 ((uint32_t)(1<<1)) |
| #define | I2S_STATE_DMA2 ((uint32_t)(1<<2)) |
| #define | I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8)) |
| #define | I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16)) |
| #define | I2S_DMA1_RX_ENABLE ((uint32_t)(1)) |
| #define | I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1)) |
| #define | I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) |
| #define | I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) |
| #define | I2S_DMA2_RX_ENABLE ((uint32_t)(1)) |
| #define | I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1)) |
| #define | I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) |
| #define | I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) |
| #define | I2S_IRQ_RX_ENABLE ((uint32_t)(1)) |
| #define | I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1)) |
| #define | I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) |
| #define | I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) |
| #define | I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) |
| #define | I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) |
| #define | I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) |
| #define | I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) |
| #define | I2S_TXBITRATE(n) ((uint32_t)(n&0x3F)) |
| #define | I2S_RXBITRATE(n) ((uint32_t)(n&0x3F)) |
| #define | I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) |
| #define | I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) |
| #define | I2S_TXMODE_MCENA ((uint32_t)(1<<3)) |
| #define | I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) |
| #define | I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) |
| #define | I2S_RXMODE_MCENA ((uint32_t)(1<<3)) |
Detailed Description
Macro defines for DAO-Digital Audio Output registerDefine Documentation
| #define I2S_DAI_MONO ((uint32_t)(1<<2)) |
I2S control mono or stereo format
Definition at line 78 of file lpc17xx_i2s.h.
| #define I2S_DAI_MUTE ((uint32_t)(1<<15)) |
I2S control mute mode
Definition at line 88 of file lpc17xx_i2s.h.
| #define I2S_DAI_RESET ((uint32_t)(1<<4)) |
I2S control reset mode
Definition at line 82 of file lpc17xx_i2s.h.
| #define I2S_DAI_SLAVE ((uint32_t)(1<<5)) |
I2S control master/slave mode
Definition at line 84 of file lpc17xx_i2s.h.
| #define I2S_DAI_STOP ((uint32_t)(1<<3)) |
I2S control stop mode
Definition at line 80 of file lpc17xx_i2s.h.
| #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) |
Definition at line 75 of file lpc17xx_i2s.h.
| #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) |
Definition at line 76 of file lpc17xx_i2s.h.
| #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) |
Macro defines for DAI-Digital Audio Input register I2S wordwide - the number of bytes in data
Definition at line 74 of file lpc17xx_i2s.h.
| #define I2S_DAI_WS_HALFPERIOD | ( | n | ) | ((uint32_t)((n&0x1FF)<<6)) |
I2S word select half period minus one (9 bits)
Definition at line 86 of file lpc17xx_i2s.h.
| #define I2S_DAO_MONO ((uint32_t)(1<<2)) |
I2S control mono or stereo format
Definition at line 58 of file lpc17xx_i2s.h.
| #define I2S_DAO_MUTE ((uint32_t)(1<<15)) |
I2S control mute mode
Definition at line 68 of file lpc17xx_i2s.h.
| #define I2S_DAO_RESET ((uint32_t)(1<<4)) |
I2S control reset mode
Definition at line 62 of file lpc17xx_i2s.h.
| #define I2S_DAO_SLAVE ((uint32_t)(1<<5)) |
I2S control master/slave mode
Definition at line 64 of file lpc17xx_i2s.h.
| #define I2S_DAO_STOP ((uint32_t)(1<<3)) |
I2S control stop mode
Definition at line 60 of file lpc17xx_i2s.h.
| #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) |
Definition at line 55 of file lpc17xx_i2s.h.
| #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) |
Definition at line 56 of file lpc17xx_i2s.h.
| #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) |
I2S wordwide - the number of bytes in data
Definition at line 54 of file lpc17xx_i2s.h.
| #define I2S_DAO_WS_HALFPERIOD | ( | n | ) | ((uint32_t)(n<<6)) |
I2S word select half period minus one
Definition at line 66 of file lpc17xx_i2s.h.
| #define I2S_DMA1_RX_DEPTH | ( | n | ) | ((uint32_t)((n&0x1F)<<8)) |
I2S set FIFO level that trigger a receive DMA request on DMA1
Definition at line 112 of file lpc17xx_i2s.h.
| #define I2S_DMA1_RX_ENABLE ((uint32_t)(1)) |
Macro defines for DMA1 register (DMA1 Configuration register) I2S control DMA1 for I2S receive
Definition at line 108 of file lpc17xx_i2s.h.
| #define I2S_DMA1_TX_DEPTH | ( | n | ) | ((uint32_t)((n&0x1F)<<16)) |
I2S set FIFO level that trigger a transmit DMA request on DMA1
Definition at line 114 of file lpc17xx_i2s.h.
| #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1)) |
I2S control DMA1 for I2S transmit
Definition at line 110 of file lpc17xx_i2s.h.
| #define I2S_DMA2_RX_DEPTH | ( | n | ) | ((uint32_t)((n&0x1F)<<8)) |
I2S set FIFO level that trigger a receive DMA request on DMA1
Definition at line 124 of file lpc17xx_i2s.h.
| #define I2S_DMA2_RX_ENABLE ((uint32_t)(1)) |
Macro defines for DMA2 register (DMA2 Configuration register) I2S control DMA2 for I2S receive
Definition at line 120 of file lpc17xx_i2s.h.
| #define I2S_DMA2_TX_DEPTH | ( | n | ) | ((uint32_t)((n&0x1F)<<16)) |
I2S set FIFO level that trigger a transmit DMA request on DMA1
Definition at line 126 of file lpc17xx_i2s.h.
| #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1)) |
I2S control DMA1 for I2S transmit
Definition at line 122 of file lpc17xx_i2s.h.
| #define I2S_IRQ_RX_DEPTH | ( | n | ) | ((uint32_t)((n&0x1F)<<8)) |
I2S set the FIFO level on which to create an irq request
Definition at line 136 of file lpc17xx_i2s.h.
| #define I2S_IRQ_RX_ENABLE ((uint32_t)(1)) |
Macro defines for IRQ register (Interrupt Request Control register) I2S control I2S receive interrupt
Definition at line 132 of file lpc17xx_i2s.h.
| #define I2S_IRQ_TX_DEPTH | ( | n | ) | ((uint32_t)((n&0x1F)<<16)) |
I2S set the FIFO level on which to create an irq request
Definition at line 138 of file lpc17xx_i2s.h.
| #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1)) |
I2S control I2S transmit interrupt
Definition at line 134 of file lpc17xx_i2s.h.
| #define I2S_RXBITRATE | ( | n | ) | ((uint32_t)(n&0x3F)) |
Definition at line 156 of file lpc17xx_i2s.h.
| #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) |
I2S Receive control 4-pin mode
Definition at line 170 of file lpc17xx_i2s.h.
| #define I2S_RXMODE_CLKSEL | ( | n | ) | ((uint32_t)(n&0x03)) |
I2S Receive select clock source
Definition at line 168 of file lpc17xx_i2s.h.
| #define I2S_RXMODE_MCENA ((uint32_t)(1<<3)) |
I2S Receive control the TX_MCLK output
Definition at line 172 of file lpc17xx_i2s.h.
| #define I2S_RXRATE_X_DIVIDER | ( | n | ) | ((uint32_t)((n&0xFF)<<8)) |
I2S Receive MCLK rate denominator
Definition at line 150 of file lpc17xx_i2s.h.
| #define I2S_RXRATE_Y_DIVIDER | ( | n | ) | ((uint32_t)(n&0xFF)) |
I2S Receive MCLK rate denominator
Definition at line 148 of file lpc17xx_i2s.h.
| #define I2S_STATE_DMA1 ((uint32_t)(1<<1)) |
I2S Status Receive or Transmit DMA1
Definition at line 96 of file lpc17xx_i2s.h.
| #define I2S_STATE_DMA2 ((uint32_t)(1<<2)) |
I2S Status Receive or Transmit DMA2
Definition at line 98 of file lpc17xx_i2s.h.
| #define I2S_STATE_IRQ ((uint32_t)(1)) |
Macro defines for STAT register (Status Feedback register) I2S Status Receive or Transmit Interrupt
Definition at line 94 of file lpc17xx_i2s.h.
| #define I2S_STATE_RX_LEVEL | ( | n | ) | ((uint32_t)((n&1F)<<8)) |
I2S Status Current level of the Receive FIFO (5 bits)
Definition at line 100 of file lpc17xx_i2s.h.
| #define I2S_STATE_TX_LEVEL | ( | n | ) | ((uint32_t)((n&1F)<<16)) |
I2S Status Current level of the Transmit FIFO (5 bits)
Definition at line 102 of file lpc17xx_i2s.h.
| #define I2S_TXBITRATE | ( | n | ) | ((uint32_t)(n&0x3F)) |
Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
Definition at line 155 of file lpc17xx_i2s.h.
| #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) |
I2S Transmit control 4-pin mode
Definition at line 164 of file lpc17xx_i2s.h.
| #define I2S_TXMODE_CLKSEL | ( | n | ) | ((uint32_t)(n&0x03)) |
Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register) I2S Transmit select clock source (2 bits)
Definition at line 162 of file lpc17xx_i2s.h.
| #define I2S_TXMODE_MCENA ((uint32_t)(1<<3)) |
I2S Transmit control the TX_MCLK output
Definition at line 166 of file lpc17xx_i2s.h.
| #define I2S_TXRATE_X_DIVIDER | ( | n | ) | ((uint32_t)((n&0xFF)<<8)) |
I2S Transmit MCLK rate denominator
Definition at line 146 of file lpc17xx_i2s.h.
| #define I2S_TXRATE_Y_DIVIDER | ( | n | ) | ((uint32_t)(n&0xFF)) |
Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register) I2S Transmit MCLK rate denominator
Definition at line 144 of file lpc17xx_i2s.h.
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