UART_REGISTER_BIT_DEFINITIONS
[UART_Private_Macros]
Defines | |
#define | UART_ACCEPTED_BAUDRATE_ERROR (3) |
#define | UART_RBR_MASKBIT ((uint8_t)0xFF) |
#define | UART_THR_MASKBIT ((uint8_t)0xFF) |
#define | UART_LOAD_DLL(div) ((div) & 0xFF) |
#define | UART_DLL_MASKBIT ((uint8_t)0xFF) |
#define | UART_DLM_MASKBIT ((uint8_t)0xFF) |
#define | UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) |
#define | UART_IER_RBRINT_EN ((uint32_t)(1<<0)) |
#define | UART_IER_THREINT_EN ((uint32_t)(1<<1)) |
#define | UART_IER_RLSINT_EN ((uint32_t)(1<<2)) |
#define | UART1_IER_MSINT_EN ((uint32_t)(1<<3)) |
#define | UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) |
#define | UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) |
#define | UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) |
#define | UART_IER_BITMASK ((uint32_t)(0x307)) |
#define | UART1_IER_BITMASK ((uint32_t)(0x38F)) |
#define | UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) |
#define | UART_IIR_INTID_RLS ((uint32_t)(3<<1)) |
#define | UART_IIR_INTID_RDA ((uint32_t)(2<<1)) |
#define | UART_IIR_INTID_CTI ((uint32_t)(6<<1)) |
#define | UART_IIR_INTID_THRE ((uint32_t)(1<<1)) |
#define | UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) |
#define | UART_IIR_INTID_MASK ((uint32_t)(7<<1)) |
#define | UART_IIR_FIFO_EN ((uint32_t)(3<<6)) |
#define | UART_IIR_ABEO_INT ((uint32_t)(1<<8)) |
#define | UART_IIR_ABTO_INT ((uint32_t)(1<<9)) |
#define | UART_IIR_BITMASK ((uint32_t)(0x3CF)) |
#define | UART_FCR_FIFO_EN ((uint8_t)(1<<0)) |
#define | UART_FCR_RX_RS ((uint8_t)(1<<1)) |
#define | UART_FCR_TX_RS ((uint8_t)(1<<2)) |
#define | UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) |
#define | UART_FCR_TRG_LEV0 ((uint8_t)(0)) |
#define | UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) |
#define | UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) |
#define | UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) |
#define | UART_FCR_BITMASK ((uint8_t)(0xCF)) |
#define | UART_TX_FIFO_SIZE (16) |
#define | UART_LCR_WLEN5 ((uint8_t)(0)) |
#define | UART_LCR_WLEN6 ((uint8_t)(1<<0)) |
#define | UART_LCR_WLEN7 ((uint8_t)(2<<0)) |
#define | UART_LCR_WLEN8 ((uint8_t)(3<<0)) |
#define | UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) |
#define | UART_LCR_PARITY_EN ((uint8_t)(1<<3)) |
#define | UART_LCR_PARITY_ODD ((uint8_t)(0)) |
#define | UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) |
#define | UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) |
#define | UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) |
#define | UART_LCR_BREAK_EN ((uint8_t)(1<<6)) |
#define | UART_LCR_DLAB_EN ((uint8_t)(1<<7)) |
#define | UART_LCR_BITMASK ((uint8_t)(0xFF)) |
#define | UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) |
#define | UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) |
#define | UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) |
#define | UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) |
#define | UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) |
#define | UART1_MCR_BITMASK ((uint8_t)(0x0F3)) |
#define | UART_LSR_RDR ((uint8_t)(1<<0)) |
#define | UART_LSR_OE ((uint8_t)(1<<1)) |
#define | UART_LSR_PE ((uint8_t)(1<<2)) |
#define | UART_LSR_FE ((uint8_t)(1<<3)) |
#define | UART_LSR_BI ((uint8_t)(1<<4)) |
#define | UART_LSR_THRE ((uint8_t)(1<<5)) |
#define | UART_LSR_TEMT ((uint8_t)(1<<6)) |
#define | UART_LSR_RXFE ((uint8_t)(1<<7)) |
#define | UART_LSR_BITMASK ((uint8_t)(0xFF)) |
#define | UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) |
#define | UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) |
#define | UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) |
#define | UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) |
#define | UART1_MSR_CTS ((uint8_t)(1<<4)) |
#define | UART1_MSR_DSR ((uint8_t)(1<<5)) |
#define | UART1_MSR_RI ((uint8_t)(1<<6)) |
#define | UART1_MSR_DCD ((uint8_t)(1<<7)) |
#define | UART1_MSR_BITMASK ((uint8_t)(0xFF)) |
#define | UART_SCR_BIMASK ((uint8_t)(0xFF)) |
#define | UART_ACR_START ((uint32_t)(1<<0)) |
#define | UART_ACR_MODE ((uint32_t)(1<<1)) |
#define | UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) |
#define | UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) |
#define | UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) |
#define | UART_ACR_BITMASK ((uint32_t)(0x307)) |
#define | UART_ICR_IRDAEN ((uint32_t)(1<<0)) |
#define | UART_ICR_IRDAINV ((uint32_t)(1<<1)) |
#define | UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) |
#define | UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) |
#define | UART_ICR_BITMASK ((uint32_t)(0x3F)) |
#define | UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) |
#define | UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) |
#define | UART_FDR_BITMASK ((uint32_t)(0xFF)) |
#define | UART_TER_TXEN ((uint8_t)(1<<7)) |
#define | UART_TER_BITMASK ((uint8_t)(0x80)) |
#define | UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) |
#define | UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) |
#define | UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) |
#define | UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) |
#define | UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) |
#define | UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) |
#define | UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) |
#define | UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) |
#define | UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) |
#define | UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) |
#define | UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) |
#define | UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) |
Define Documentation
#define UART1_IER_BITMASK ((uint32_t)(0x38F)) |
UART1 interrupt enable register bit mask
Definition at line 78 of file lpc17xx_uart.h.
#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) |
CTS1 signal transition interrupt enable
Definition at line 74 of file lpc17xx_uart.h.
#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) |
Modem status interrupt enable
Definition at line 73 of file lpc17xx_uart.h.
#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) |
Interrupt identification: Modem interrupt
Definition at line 87 of file lpc17xx_uart.h.
#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) |
Enable Auto CTS flow-control
Definition at line 128 of file lpc17xx_uart.h.
#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) |
Enable Auto RTS flow-control
Definition at line 127 of file lpc17xx_uart.h.
#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) |
UART1 bit mask value
Definition at line 129 of file lpc17xx_uart.h.
#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) |
Source for modem output pin DTR
Definition at line 124 of file lpc17xx_uart.h.
#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) |
Loop back mode select
Definition at line 126 of file lpc17xx_uart.h.
#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) |
Source for modem output pin RTS
Definition at line 125 of file lpc17xx_uart.h.
#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) |
MSR register bit-mask value
Definition at line 153 of file lpc17xx_uart.h.
#define UART1_MSR_CTS ((uint8_t)(1<<4)) |
Clear To Send State
Definition at line 149 of file lpc17xx_uart.h.
#define UART1_MSR_DCD ((uint8_t)(1<<7)) |
Data Carrier Detect State
Definition at line 152 of file lpc17xx_uart.h.
#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) |
Set upon state change of input CTS
Definition at line 145 of file lpc17xx_uart.h.
#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) |
Set upon state change of input DCD
Definition at line 148 of file lpc17xx_uart.h.
#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) |
Set upon state change of input DSR
Definition at line 146 of file lpc17xx_uart.h.
#define UART1_MSR_DSR ((uint8_t)(1<<5)) |
Data Set Ready State
Definition at line 150 of file lpc17xx_uart.h.
#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) |
Set upon low to high transition of input RI
Definition at line 147 of file lpc17xx_uart.h.
#define UART1_MSR_RI ((uint8_t)(1<<6)) |
Ring Indicator State
Definition at line 151 of file lpc17xx_uart.h.
#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) |
Bit mask value
Definition at line 199 of file lpc17xx_uart.h.
#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) |
Auto Address Detect (AAD) is enabled
Definition at line 188 of file lpc17xx_uart.h.
#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) |
RS485 control bit-mask value
Definition at line 195 of file lpc17xx_uart.h.
#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) |
Enable Auto Direction Control
Definition at line 191 of file lpc17xx_uart.h.
#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) |
RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled
Definition at line 185 of file lpc17xx_uart.h.
#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) |
This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. The direction control pin will be driven to logic "1" when the transmitter has data to be sent
Definition at line 192 of file lpc17xx_uart.h.
#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) |
The receiver is disabled
Definition at line 187 of file lpc17xx_uart.h.
#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) |
If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control
Definition at line 189 of file lpc17xx_uart.h.
#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) |
Definition at line 202 of file lpc17xx_uart.h.
#define UART_ACCEPTED_BAUDRATE_ERROR (3) |
Acceptable UART baudrate error
Definition at line 52 of file lpc17xx_uart.h.
#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) |
UART End of auto-baud interrupt clear
Definition at line 163 of file lpc17xx_uart.h.
#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) |
UART Auto-baud time-out interrupt clear
Definition at line 164 of file lpc17xx_uart.h.
#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) |
UART Auto baudrate restart
Definition at line 162 of file lpc17xx_uart.h.
#define UART_ACR_BITMASK ((uint32_t)(0x307)) |
UART Auto Baudrate register bit mask
Definition at line 165 of file lpc17xx_uart.h.
#define UART_ACR_MODE ((uint32_t)(1<<1)) |
UART Auto baudrate Mode 1
Definition at line 161 of file lpc17xx_uart.h.
#define UART_ACR_START ((uint32_t)(1<<0)) |
UART Auto-baud start
Definition at line 160 of file lpc17xx_uart.h.
#define UART_DLL_MASKBIT ((uint8_t)0xFF) |
Divisor latch LSB bit mask
Definition at line 62 of file lpc17xx_uart.h.
#define UART_DLM_MASKBIT ((uint8_t)0xFF) |
Divisor latch MSB bit mask
Definition at line 65 of file lpc17xx_uart.h.
#define UART_FCR_BITMASK ((uint8_t)(0xCF)) |
UART FIFO control bit mask
Definition at line 104 of file lpc17xx_uart.h.
#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) |
UART DMA mode selection
Definition at line 99 of file lpc17xx_uart.h.
#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) |
UART FIFO enable
Definition at line 96 of file lpc17xx_uart.h.
#define UART_FCR_RX_RS ((uint8_t)(1<<1)) |
UART FIFO RX reset
Definition at line 97 of file lpc17xx_uart.h.
#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) |
UART FIFO trigger level 0: 1 character
Definition at line 100 of file lpc17xx_uart.h.
#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) |
UART FIFO trigger level 1: 4 character
Definition at line 101 of file lpc17xx_uart.h.
#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) |
UART FIFO trigger level 2: 8 character
Definition at line 102 of file lpc17xx_uart.h.
#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) |
UART FIFO trigger level 3: 14 character
Definition at line 103 of file lpc17xx_uart.h.
#define UART_FCR_TX_RS ((uint8_t)(1<<2)) |
UART FIFO TX reset
Definition at line 98 of file lpc17xx_uart.h.
#define UART_FDR_BITMASK ((uint32_t)(0xFF)) |
UART Fractional Divider register bit mask
Definition at line 177 of file lpc17xx_uart.h.
#define UART_FDR_DIVADDVAL | ( | n | ) | ((uint32_t)(n&0x0F)) |
Baud-rate generation pre-scaler divisor
Definition at line 175 of file lpc17xx_uart.h.
#define UART_FDR_MULVAL | ( | n | ) | ((uint32_t)((n<<4)&0xF0)) |
Baud-rate pre-scaler multiplier value
Definition at line 176 of file lpc17xx_uart.h.
#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) |
UART FIFO Level Register bit mask
Definition at line 208 of file lpc17xx_uart.h.
#define UART_FIFOLVL_RXFIFOLVL | ( | n | ) | ((uint32_t)(n&0x0F)) |
Reflects the current level of the UART receiver FIFO
Definition at line 206 of file lpc17xx_uart.h.
#define UART_FIFOLVL_TXFIFOLVL | ( | n | ) | ((uint32_t)((n>>8)&0x0F)) |
Reflects the current level of the UART transmitter FIFO
Definition at line 207 of file lpc17xx_uart.h.
#define UART_ICR_BITMASK ((uint32_t)(0x3F)) |
UART IRDA bit mask
Definition at line 172 of file lpc17xx_uart.h.
#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) |
IrDA fixed pulse width mode
Definition at line 170 of file lpc17xx_uart.h.
#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) |
IrDA mode enable
Definition at line 168 of file lpc17xx_uart.h.
#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) |
IrDA serial input inverted
Definition at line 169 of file lpc17xx_uart.h.
#define UART_ICR_PULSEDIV | ( | n | ) | ((uint32_t)((n&0x07)<<3)) |
PulseDiv - Configures the pulse when FixPulseEn = 1
Definition at line 171 of file lpc17xx_uart.h.
#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) |
Enables the end of auto-baud interrupt
Definition at line 75 of file lpc17xx_uart.h.
#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) |
Enables the auto-baud time-out interrupt
Definition at line 76 of file lpc17xx_uart.h.
#define UART_IER_BITMASK ((uint32_t)(0x307)) |
UART interrupt enable register bit mask
Definition at line 77 of file lpc17xx_uart.h.
#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) |
RBR Interrupt enable
Definition at line 70 of file lpc17xx_uart.h.
#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) |
RX line status interrupt enable
Definition at line 72 of file lpc17xx_uart.h.
#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) |
THR Interrupt enable
Definition at line 71 of file lpc17xx_uart.h.
#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) |
End of auto-baud interrupt
Definition at line 90 of file lpc17xx_uart.h.
#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) |
Auto-baud time-out interrupt
Definition at line 91 of file lpc17xx_uart.h.
#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) |
UART interrupt identification register bit mask
Definition at line 92 of file lpc17xx_uart.h.
#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) |
These bits are equivalent to UnFCR[0]
Definition at line 89 of file lpc17xx_uart.h.
#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) |
Interrupt identification: Character time-out indicator
Definition at line 85 of file lpc17xx_uart.h.
#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) |
Interrupt identification: Interrupt ID mask
Definition at line 88 of file lpc17xx_uart.h.
#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) |
Interrupt identification: Receive data available
Definition at line 84 of file lpc17xx_uart.h.
#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) |
Interrupt identification: Receive line status
Definition at line 83 of file lpc17xx_uart.h.
#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) |
Interrupt identification: THRE interrupt
Definition at line 86 of file lpc17xx_uart.h.
#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) |
Interrupt Status - Active low
Definition at line 82 of file lpc17xx_uart.h.
#define UART_LCR_BITMASK ((uint8_t)(0xFF)) |
UART line control bit mask
Definition at line 120 of file lpc17xx_uart.h.
#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) |
UART Transmission Break enable
Definition at line 118 of file lpc17xx_uart.h.
#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) |
UART Divisor Latches Access bit enable
Definition at line 119 of file lpc17xx_uart.h.
#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) |
UART Parity Enable
Definition at line 113 of file lpc17xx_uart.h.
#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) |
UART Even Parity Select
Definition at line 115 of file lpc17xx_uart.h.
#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) |
UART force 0 stick parity
Definition at line 117 of file lpc17xx_uart.h.
#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) |
UART force 1 stick parity
Definition at line 116 of file lpc17xx_uart.h.
#define UART_LCR_PARITY_ODD ((uint8_t)(0)) |
UART Odd Parity Select
Definition at line 114 of file lpc17xx_uart.h.
#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) |
UART Two Stop Bits Select
Definition at line 112 of file lpc17xx_uart.h.
#define UART_LCR_WLEN5 ((uint8_t)(0)) |
UART 5 bit data mode
Definition at line 108 of file lpc17xx_uart.h.
#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) |
UART 6 bit data mode
Definition at line 109 of file lpc17xx_uart.h.
#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) |
UART 7 bit data mode
Definition at line 110 of file lpc17xx_uart.h.
#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) |
UART 8 bit data mode
Definition at line 111 of file lpc17xx_uart.h.
#define UART_LOAD_DLL | ( | div | ) | ((div) & 0xFF) |
Macro for loading least significant halfs of divisors
Definition at line 61 of file lpc17xx_uart.h.
#define UART_LOAD_DLM | ( | div | ) | (((div) >> 8) & 0xFF) |
Macro for loading most significant halfs of divisors
Definition at line 66 of file lpc17xx_uart.h.
#define UART_LSR_BI ((uint8_t)(1<<4)) |
Line status register: Break interrupt
Definition at line 137 of file lpc17xx_uart.h.
#define UART_LSR_BITMASK ((uint8_t)(0xFF)) |
UART Line status bit mask
Definition at line 141 of file lpc17xx_uart.h.
#define UART_LSR_FE ((uint8_t)(1<<3)) |
Line status register: Framing error
Definition at line 136 of file lpc17xx_uart.h.
#define UART_LSR_OE ((uint8_t)(1<<1)) |
Line status register: Overrun error
Definition at line 134 of file lpc17xx_uart.h.
#define UART_LSR_PE ((uint8_t)(1<<2)) |
Line status register: Parity error
Definition at line 135 of file lpc17xx_uart.h.
#define UART_LSR_RDR ((uint8_t)(1<<0)) |
Line status register: Receive data ready
Definition at line 133 of file lpc17xx_uart.h.
#define UART_LSR_RXFE ((uint8_t)(1<<7)) |
Error in RX FIFO
Definition at line 140 of file lpc17xx_uart.h.
#define UART_LSR_TEMT ((uint8_t)(1<<6)) |
Line status register: Transmitter empty
Definition at line 139 of file lpc17xx_uart.h.
#define UART_LSR_THRE ((uint8_t)(1<<5)) |
Line status register: Transmit holding register empty
Definition at line 138 of file lpc17xx_uart.h.
#define UART_RBR_MASKBIT ((uint8_t)0xFF) |
UART Received Buffer mask bit (8 bits)
Definition at line 55 of file lpc17xx_uart.h.
#define UART_SCR_BIMASK ((uint8_t)(0xFF)) |
UART Scratch Pad bit mask
Definition at line 157 of file lpc17xx_uart.h.
#define UART_TER_BITMASK ((uint8_t)(0x80)) |
UART Transmit Enable Register bit mask
Definition at line 181 of file lpc17xx_uart.h.
#define UART_TER_TXEN ((uint8_t)(1<<7)) |
Transmit enable bit
Definition at line 180 of file lpc17xx_uart.h.
#define UART_THR_MASKBIT ((uint8_t)0xFF) |
UART Transmit Holding mask bit (8 bits)
Definition at line 58 of file lpc17xx_uart.h.
#define UART_TX_FIFO_SIZE (16) |
Definition at line 105 of file lpc17xx_uart.h.
Generated on Mon Feb 8 10:01:48 2010 for LPC1700CMSIS Standard Peripheral Firmware Library by 1.5.9