PWM_REGISTER_BIT_DEFINITIONS
[PWM_Private_Macros]
Defines | |
#define | PWM_IR_PWMMRn(n) ((uint32_t)((n<4)?(1<<n):(1<<(n+4)))) |
#define | PWM_IR_PWMCAPn(n) ((uint32_t)(1<<(n+4))) |
#define | PWM_IR_BITMASK ((uint32_t)(0x0000073F)) |
#define | PWM_TCR_BITMASK ((uint32_t)(0x0000000B)) |
#define | PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0)) |
#define | PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1)) |
#define | PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3)) |
#define | PWM_CTCR_BITMASK ((uint32_t)(0x0000000F)) |
#define | PWM_CTCR_MODE(n) ((uint32_t)(n&0x03)) |
#define | PWM_CTCR_SELECT_INPUT(n) ((uint32_t)((n&0x03)<<2)) |
#define | PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF)) |
#define | PWM_MCR_INT_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)))) |
#define | PWM_MCR_RESET_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1))) |
#define | PWM_MCR_STOP_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2))) |
#define | PWM_CCR_BITMASK ((uint32_t)(0x0000003F)) |
#define | PWM_CCR_CAP_RISING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)))) |
#define | PWM_CCR_CAP_FALLING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1))) |
#define | PWM_CCR_INT_ON_CAP(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2))) |
#define | PWM_PCR_BITMASK (uint32_t)0x00007E7C |
#define | PWM_PCR_PWMSELn(n) ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n))) |
#define | PWM_PCR_PWMENAn(n) ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8)))) |
#define | PWM_LER_BITMASK ((uint32_t)(0x0000007F)) |
#define | PWM_LER_EN_MATCHn_LATCH(n) ((uint32_t)((n<7) ? (1<<n) : 0)) |
Define Documentation
#define PWM_CCR_BITMASK ((uint32_t)(0x0000003F)) |
CCR register mask
Definition at line 99 of file lpc17xx_pwm.h.
#define PWM_CCR_CAP_FALLING | ( | n | ) | ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1))) |
PCAPn is falling edge sensitive
Definition at line 103 of file lpc17xx_pwm.h.
#define PWM_CCR_CAP_RISING | ( | n | ) | ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)))) |
PCAPn is rising edge sensitive
Definition at line 101 of file lpc17xx_pwm.h.
#define PWM_CCR_INT_ON_CAP | ( | n | ) | ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2))) |
PWM interrupt is generated on a PCAP event
Definition at line 105 of file lpc17xx_pwm.h.
#define PWM_CTCR_BITMASK ((uint32_t)(0x0000000F)) |
CTCR register mask
Definition at line 75 of file lpc17xx_pwm.h.
#define PWM_CTCR_MODE | ( | n | ) | ((uint32_t)(n&0x03)) |
PWM Counter-Timer Mode
Definition at line 77 of file lpc17xx_pwm.h.
#define PWM_CTCR_SELECT_INPUT | ( | n | ) | ((uint32_t)((n&0x03)<<2)) |
PWM Capture input select
Definition at line 79 of file lpc17xx_pwm.h.
#define PWM_IR_BITMASK ((uint32_t)(0x0000073F)) |
IR register mask
Definition at line 58 of file lpc17xx_pwm.h.
#define PWM_IR_PWMCAPn | ( | n | ) | ((uint32_t)(1<<(n+4))) |
Interrupt flag for capture input
Definition at line 56 of file lpc17xx_pwm.h.
#define PWM_IR_PWMMRn | ( | n | ) | ((uint32_t)((n<4)?(1<<n):(1<<(n+4)))) |
Interrupt flag for PWM match channel for 6 channel
Definition at line 54 of file lpc17xx_pwm.h.
#define PWM_LER_BITMASK ((uint32_t)(0x0000007F)) |
LER register mask
Definition at line 123 of file lpc17xx_pwm.h.
#define PWM_LER_EN_MATCHn_LATCH | ( | n | ) | ((uint32_t)((n<7) ? (1<<n) : 0)) |
PWM MATCHn register update control
Definition at line 125 of file lpc17xx_pwm.h.
#define PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF)) |
MCR register mask
Definition at line 86 of file lpc17xx_pwm.h.
#define PWM_MCR_INT_ON_MATCH | ( | n | ) | ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)))) |
generate a PWM interrupt when a MATCHn occurs
Definition at line 88 of file lpc17xx_pwm.h.
#define PWM_MCR_RESET_ON_MATCH | ( | n | ) | ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1))) |
reset the PWM when a MATCHn occurs
Definition at line 90 of file lpc17xx_pwm.h.
#define PWM_MCR_STOP_ON_MATCH | ( | n | ) | ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2))) |
stop the PWM when a MATCHn occurs
Definition at line 92 of file lpc17xx_pwm.h.
#define PWM_PCR_BITMASK (uint32_t)0x00007E7C |
PCR register mask
Definition at line 112 of file lpc17xx_pwm.h.
#define PWM_PCR_PWMENAn | ( | n | ) | ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8)))) |
enable PWM output n
Definition at line 116 of file lpc17xx_pwm.h.
#define PWM_PCR_PWMSELn | ( | n | ) | ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n))) |
PWM output n is a single edge controlled output
Definition at line 114 of file lpc17xx_pwm.h.
#define PWM_TCR_BITMASK ((uint32_t)(0x0000000B)) |
TCR register mask
Definition at line 65 of file lpc17xx_pwm.h.
#define PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0)) |
PWM Counter Enable
Definition at line 66 of file lpc17xx_pwm.h.
#define PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1)) |
PWM Counter Reset
Definition at line 67 of file lpc17xx_pwm.h.
#define PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3)) |
PWM Enable
Definition at line 68 of file lpc17xx_pwm.h.
Generated on Mon Feb 8 10:01:46 2010 for LPC1700CMSIS Standard Peripheral Firmware Library by 1.5.9