Clock Attributes:Update Clock Source
Short Name: Update Clock Source
This property controls the update clock source.
Default Value: NIFGEN_VAL_INTERNAL
Defined Values:
| NIFGEN_VAL_INTERNAL | Internal update clock |
| NIFGEN_VAL_EXTERNAL | External update clock given on the IO connector |
| NIFGEN_VAL_CLK_IN | Coaxial CLK IN connector on the board front panel |
| NIFGEN_VAL_DDC_CLK_IN | DDC CLK IN line of the Digital Data & Control connector |
| NIFGEN_VAL_PXI_STAR | (PXI only) PXI STAR trigger line. This choice is valid only in PXI chassis slots 3 through 15. |
| NIFGEN_VAL_RTSI_0 | RTSI line 0 |
| NIFGEN_VAL_RTSI_1 | RTSI line 1 |
| NIFGEN_VAL_RTSI_2 | RTSI line 2 |
| NIFGEN_VAL_RTSI_3 | RTSI line 3 |
| NIFGEN_VAL_RTSI_4 | RTSI line 4 |
| NIFGEN_VAL_RTSI_5 | RTSI line 5 |
| NIFGEN_VAL_RTSI_6 | RTSI line 6 |
| NIFGEN_VAL_RTSI_7 | RTSI line 7 (PCI only) |
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Note You cannot change this property while the device is generating a waveform. If you want to change the device configuration, call the niFgen Abort Generation VI or wait for the generation to complete. |
Remarks
The following table lists the characteristics of this property.
| Data Type | ViInt32 |
| Permissions | R/W |
| Channel Based | No |
| High-Level VI | niFgen Configure Update Clock Source VI |