Exported Sample Clock Divisor

LabView FGEN

Routing and Event Configuration:Exported Sample Clock Divisor

Short Name: Exported Sample Clock Divisor

Specifies the factor by which to divide the update (sample) clock before it is exported. To export the sample clock, use the niFgen Export Signal VI.

Default Value: 1

Values: Range is from 1 to 4,096

Note  You cannot change this property while the device is generating a waveform. If you want to change the device configuration, call the niFgen Abort Generation VI or wait for the generation to complete.

Remarks

The following table lists the characteristics of this property.


Data Type ViInt32
Permissions R/W
Channel Based No
High-Level VI None