Exported Sample Clock Timebase Divisor

LabView FGEN

Routing and Event Configuration:Exported Sample Clock Timebase Divisor

Short Name: Exported Sample Clock Timebase Divisor

Specifies the factor by which to divide the board clock (sample clock timebase) before it is exported. To export the sample clock timebase, use the niFgen Export Signal VI.

Default Value: 2

Values: Range is from 2 to 4,194,304.

Remarks

The following table lists the characteristics of this property.


Data Type ViInt32
Permissions R/W
Channel Based No
High-Level VI None