Clock Attributes:Reference Clock Source
Short Name: Reference Clock Source
Specifies the source for the reference clock. For example, when you set this attribute to "ClkIn," the signal generator uses the signal it receives at its Clk In front panel connector as the reference clock.
The reference clock at the specified source phase-locks with the signal generator's sample clock timebase to allow the frequency stability and accuracy of the sample clock timebase to match that of the reference clock.
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Notes The signal generator must not be in the Generating state when you change this property. To change the device configuration, call the niFgen Abort Generation VI or wait for the generation to complete. |
| The following defined values are examples of possible reference clock sources. For a complete list of the reference clock sources available on your device, refer to the Device Routes tab in MAX. |
Defined Values
| "None" | No Reference clock source |
| "PXI_Clk10" | 10 MHz reference clock signal provided by the PXI bus |
| "ClkIn" | External signal on the Clk In front panel connector |
| "OnboardRefClk" | Dedicated 10 MHz clock for PCI modules |
| "RTSI7" | RTSI line 7 |
| "RefIn" | External signal on the Ref In front panel connector |
Default Value: "None"
Remarks
The following table lists the characteristics of this property.
| Data Type | ViInt32 |
| Permissions | R/W |
| Channel Based | No |
| High-Level VI | niFgen Configure Reference Clock VI |