Clock Attributes:Sample Clock:Source
Short Name: Sample Clock Source
Specifies the Sample Clock source.
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Notes The signal generator must not be in the Generating state when you change this property. To change the device configuration, call the niFgen Abort Generation VI or wait for the generation to complete. |
| The following defined values are examples of possible sample clock sources. For a complete list of the sample clock sources available on your device, refer to the Device Routes tab in MAX. |
Defined Values
| "OnboardClock" | Onboard clock |
| "ClkIn" | Clk In front panel connector |
| "PXI_Star" | PXI Star line |
| "PXI_Trig0" | PXI or RTSI line 0 |
| "PXI_Trig1" | PXI or RTSI line 1 |
| "PXI_Trig2" | PXI or RTSI line 2 |
| "PXI_Trig3" | PXI or RTSI line 3 |
| "PXI_Trig4" | PXI or RTSI line 4 |
| "PXI_Trig5" | PXI or RTSI line 5 |
| "PXI_Trig6" | PXI or RTSI line 6 |
| "PXI_Trig7" | PXI or RTSI line 7 |
| "DDC_ClkIn" | Sample clock from DDC connector |
Default Value: "OnboardClock"
Remarks
The following table lists the characteristics of this property.
| Data Type | ViString |
| Permissions | R/W |
| Channel Based | No |
| High-Level VI | None |