niFgen Adjust Sample Clock Relative Delay
From LabView FGEN
niFgen Adjust Sample Clock Relative Delay
Delays (or phase shifts) the sample clock, which delays the output of the module. Delaying the sample clock can be useful when lining up the output of multiple modules or when intentionally phase shifting the output relative to a fixed reference such as the PLL reference clock.
Adjustment time can be positive or negative, but it must be less than or equal to the sample clock period. The delay takes effect immediately after this VI is called. To delay an external sample clock, set the Sample Clock Absolute Delay property.| Note Calling this VI after calling NI-TClk Synchronize breaks synchronization. |

| Instrument Handle identifies your instrument session. Instrument Handle was obtained from the niFgen Initialize VI or niFgen Initialize With Options VI. | |||||||
| Adjustment Time specifies the amount of time to adjust the sample clock delay.
Units: Seconds (s) |
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error in describes error conditions that occur before this VI or function runs.
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| Instrument Handle Out passes a reference to your instrument session to the next VI. | |||||||
error out contains error information. If error in indicates that an error occurred before this VI or function ran, error out contains the same error information. Otherwise, it describes the error status that this VI or function produces.
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