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LPC1700CMSIS Standard Peripheral Firmware Library: C:/nxpdrv/LPC1700CMSIS/Core/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c Source File

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C:/nxpdrv/LPC1700CMSIS/Core/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c

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/**************************************************************************/
#include <stdint.h>
#include "LPC17xx.h"

/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/

/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
//   <h> System Controls and Status Register (SCS)
//     <o1.4>    OSCRANGE: Main Oscillator Range Select
//                     <0=>  1 MHz to 20 MHz
//                     <1=> 15 MHz to 24 MHz
//     <e1.5>       OSCEN: Main Oscillator Enable
//     </e>
//   </h>
//
//   <h> Clock Source Select Register (CLKSRCSEL)
//     <o2.0..1>   CLKSRC: PLL Clock Source Selection
//                     <0=> Internal RC oscillator
//                     <1=> Main oscillator
//                     <2=> RTC oscillator
//   </h>
//
//   <e3> PLL0 Configuration (Main PLL)
//     <h> PLL0 Configuration Register (PLL0CFG)
//                     <i> F_cco0 = (2 * M * F_in) / N
//                     <i> F_in must be in the range of 32 kHz to 50 MHz
//                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
//       <o4.0..14>  MSEL: PLL Multiplier Selection
//                     <6-32768><#-1>
//                     <i> M Value
//       <o4.16..23> NSEL: PLL Divider Selection
//                     <1-256><#-1>
//                     <i> N Value
//     </h>
//   </e>
//
//   <e5> PLL1 Configuration (USB PLL)
//     <h> PLL1 Configuration Register (PLL1CFG)
//                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
//                     <i> F_cco1 = F_osc * M * 2 * P
//                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
//       <o6.0..4>   MSEL: PLL Multiplier Selection
//                     <1-32><#-1>
//                     <i> M Value (for USB maximum value is 4)
//       <o6.5..6>   PSEL: PLL Divider Selection
//                     <0=> 1
//                     <1=> 2
//                     <2=> 4
//                     <3=> 8
//                     <i> P Value
//     </h>
//   </e>
//
//   <h> CPU Clock Configuration Register (CCLKCFG)
//     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
//                     <3-256><#-1>
//   </h>
//
//   <h> USB Clock Configuration Register (USBCLKCFG)
//     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL0
//                     <0-15>
//                     <i> Divide is USBSEL + 1
//   </h>
//
//   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
//     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 6
//     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 6
//     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 6
//   </h>
//
//   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
//     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
//                     <0=> Pclk = Cclk / 4
//                     <1=> Pclk = Cclk
//                     <2=> Pclk = Cclk / 2
//                     <3=> Pclk = Hclk / 8
//   </h>
//
//   <h> Power Control for Peripherals Register (PCONP)
//     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
//     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
//     <o11.3>      PCUART0: UART 0 power/clock enable
//     <o11.4>      PCUART1: UART 1 power/clock enable
//     <o11.6>      PCPWM1: PWM 1 power/clock enable
//     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
//     <o11.8>      PCSPI: SPI interface power/clock enable
//     <o11.9>      PCRTC: RTC power/clock enable
//     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
//     <o11.12>     PCAD: A/D converter power/clock enable
//     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
//     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
//     <o11.15>     PCGPIO: GPIOs power/clock enable
//     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
//     <o11.17>     PCMC: Motor control PWM power/clock enable
//     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
//     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
//     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
//     <o11.22>     PCTIM2: Timer 2 power/clock enable
//     <o11.23>     PCTIM3: Timer 3 power/clock enable
//     <o11.24>     PCUART2: UART 2 power/clock enable
//     <o11.25>     PCUART3: UART 3 power/clock enable
//     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
//     <o11.27>     PCI2S: I2S interface power/clock enable
//     <o11.29>     PCGPDMA: GP DMA function power/clock enable
//     <o11.30>     PCENET: Ethernet block power/clock enable
//     <o11.31>     PCUSB: USB interface power/clock enable
//   </h>
//
//   <h> Clock Output Configuration Register (CLKOUTCFG)
//     <o12.0..3>   CLKOUTSEL: Selects clock source for CLKOUT
//                     <0=> CPU clock
//                     <1=> Main oscillator
//                     <2=> Internal RC oscillator
//                     <3=> USB clock
//                     <4=> RTC oscillator
//     <o12.4..7>   CLKOUTDIV: Selects clock divider for CLKOUT
//                     <1-16><#-1>
//     <o12.8>      CLKOUT_EN: CLKOUT enable control
//   </h>
//
// </e>
*/
#define CLOCK_SETUP           1
#define SCS_Val               0x00000020
#define CLKSRCSEL_Val         0x00000001
#define PLL0_SETUP            1
#define PLL0CFG_Val           0x00050063
#define PLL1_SETUP            1
#define PLL1CFG_Val           0x00000023
#define CCLKCFG_Val           0x00000003
#define USBCLKCFG_Val         0x00000000
#define PCLKSEL0_Val          0x00000000
#define PCLKSEL1_Val          0x00000000
#define PCONP_Val             0x042887DE
#define CLKOUTCFG_Val         0x00000000


/*--------------------- Flash Accelerator Configuration ----------------------
//
// <e> Flash Accelerator Configuration
//   <o1.0..11>  Reserved
//   <o1.12..15> FLASHTIM: Flash Access Time
//               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
//               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
//               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
//               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
//               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
//               <5=> 6 CPU clocks (for any CPU clock)
// </e>
*/
#define FLASH_SETUP           1
#define FLASHCFG_Val          0x0000303A

/*
//-------- <<< end of configuration section >>> ------------------------------
*/

/*----------------------------------------------------------------------------
  Check the register settings
 *----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
#define CHECK_RSVD(val, mask)                     (val & mask)

/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SCS_Val),       ~0x00000030))
   #error "SCS: Invalid values of reserved bits!"
#endif

#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
   #error "CLKSRCSEL: Value out of range!"
#endif

#if (CHECK_RSVD((PLL0CFG_Val),   ~0x00FF7FFF))
   #error "PLL0CFG: Invalid values of reserved bits!"
#endif

#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
   #error "PLL1CFG: Invalid values of reserved bits!"
#endif

#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
   #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
#endif

#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
   #error "USBCLKCFG: Invalid values of reserved bits!"
#endif

#if (CHECK_RSVD((PCLKSEL0_Val),   0x000C0C00))
   #error "PCLKSEL0: Invalid values of reserved bits!"
#endif

#if (CHECK_RSVD((PCLKSEL1_Val),   0x03000300))
   #error "PCLKSEL1: Invalid values of reserved bits!"
#endif

#if (CHECK_RSVD((PCONP_Val),      0x10100821))
   #error "PCONP: Invalid values of reserved bits!"
#endif

#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
   #error "CLKOUTCFG: Invalid values of reserved bits!"
#endif

/* Flash Accelerator Configuration -------------------------------------------*/
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
   #error "FLASHCFG: Invalid values of reserved bits!"
#endif


/*----------------------------------------------------------------------------
  DEFINES
 *----------------------------------------------------------------------------*/

/*----------------------------------------------------------------------------
  Define clocks
 *----------------------------------------------------------------------------*/
#define XTAL        (12000000UL)        /* Oscillator frequency               */
#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
#define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
#define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */


/* F_cco0 = (2 * M * F_in) / N  */
#define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1)
#define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
#define __FCCO(__F_IN)    ((2 * __M * __F_IN) / __N)
#define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1)

/* Determine core clock frequency according to settings */
 #if (PLL0_SETUP)
    #if   ((CLKSRCSEL_Val & 0x03) == 1)
        #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
    #elif ((CLKSRCSEL_Val & 0x03) == 2)
        #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
    #else
        #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
    #endif
 #else
    #if   ((CLKSRCSEL_Val & 0x03) == 1)
        #define __CORE_CLK (OSC_CLK         / __CCLK_DIV)
    #elif ((CLKSRCSEL_Val & 0x03) == 2)
        #define __CORE_CLK (RTC_CLK         / __CCLK_DIV)
    #else
        #define __CORE_CLK (IRC_OSC         / __CCLK_DIV)
    #endif
 #endif


/*----------------------------------------------------------------------------
  Clock Variable definitions
 *----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __CORE_CLK;
/*----------------------------------------------------------------------------
  Clock functions
 *----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
{
  /* Determine clock frequency according to clock register values             */
  if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
    switch (LPC_SC->CLKSRCSEL & 0x03) {
      case 0:                                /* Int. RC oscillator => PLL0    */
      case 3:                                /* Reserved, default to Int. RC  */
        SystemCoreClock = (IRC_OSC *
                          ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    /
                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
        break;
      case 1:                                /* Main oscillator => PLL0       */
        SystemCoreClock = (OSC_CLK *
                          ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    /
                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
        break;
      case 2:                                /* RTC oscillator => PLL0        */
        SystemCoreClock = (RTC_CLK *
                          ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    /
                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
        break;
    }
  } else {
    switch (LPC_SC->CLKSRCSEL & 0x03) {
      case 0:                                /* Int. RC oscillator => PLL0    */
      case 3:                                /* Reserved, default to Int. RC  */
        SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
        break;
      case 1:                                /* Main oscillator => PLL0       */
        SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
        break;
      case 2:                                /* RTC oscillator => PLL0        */
        SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
        break;
    }
  }

}
/* Exported types --------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
//extern unsigned long _sidata;         /* start address for the initialization values of the .data section. defined in linker script */
//extern unsigned long _sdata;          /* start address for the .data section. defined in linker script */
//extern unsigned long _edata;          /* end address for the .data section. defined in linker script */
//
//extern unsigned long _sbss;                   /* start address for the .bss section. defined in linker script */
//extern unsigned long _ebss;                   /* end address for the .bss section. defined in linker script */

//void _init(void)
//{
//    unsigned long *pulSrc, *pulDest;
//
//    //
//    // Copy the data segment initializers from flash to SRAM in ROM mode
//    //
//#if (__RAM_MODE__==0)
//    pulSrc = &_sidata;
//    for(pulDest = &_sdata; pulDest < &_edata; )
//    {
//        *(pulDest++) = *(pulSrc++);
//    }
//#endif
//
//
//    //
//    // Zero fill the bss segment.
//    //
//    for(pulDest = &_sbss; pulDest < &_ebss; )
//    {
//        *(pulDest++) = 0;
//    }
//}

void SystemInit (void)
{

#if (CLOCK_SETUP)                       /* Clock Setup                        */
  LPC_SC->SCS       = SCS_Val;
  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
  }

  LPC_SC->CCLKCFG   = CCLKCFG_Val;      /* Setup Clock Divider                */
  LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     /* Peripheral Clock Selection         */
  LPC_SC->PCLKSEL1  = PCLKSEL1_Val;

#if (PLL0_SETUP)
  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for PLL0       */

  LPC_SC->PLL0CFG   = PLL0CFG_Val;      /* configure PLL0                     */
  LPC_SC->PLL0FEED  = 0xAA;
  LPC_SC->PLL0FEED  = 0x55;

  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
  LPC_SC->PLL0FEED  = 0xAA;
  LPC_SC->PLL0FEED  = 0x55;
  while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0                    */

  LPC_SC->PLL0CON   = 0x03;             /* PLL0 Enable & Connect              */
  LPC_SC->PLL0FEED  = 0xAA;
  LPC_SC->PLL0FEED  = 0x55;
  while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
#endif

#if (PLL1_SETUP)
  LPC_SC->PLL1CFG   = PLL1CFG_Val;
  LPC_SC->PLL1FEED  = 0xAA;
  LPC_SC->PLL1FEED  = 0x55;

  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
  LPC_SC->PLL1FEED  = 0xAA;
  LPC_SC->PLL1FEED  = 0x55;
  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */

  LPC_SC->PLL1CON   = 0x03;             /* PLL1 Enable & Connect              */
  LPC_SC->PLL1FEED  = 0xAA;
  LPC_SC->PLL1FEED  = 0x55;
  while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
#else
  LPC_SC->USBCLKCFG = USBCLKCFG_Val;    /* Setup USB Clock Divider            */
#endif
  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */

  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
#endif

#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
  LPC_SC->FLASHCFG  = FLASHCFG_Val;
#endif
}

---

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• LPC1700CMSIS Standard Peripheral Firmware Library
• LPC1700CMSIS Source List
• LPC1700CMSIS Driver Firmware Library Release Note
• Modules
  • CMSIS
    • LPC17xx
      • CMSIS_Configuration
      • Peripheral_register_structures
      • Peripheral_memory_map
      • Peripheral_declaration
    • LPC17xx_System
      • LPC17xx_System_Defines
      • LPC17xx_System_Public_Variables
      • LPC17xx_System_Public_Functions
  • LPC1700CMSIS_FwLib_Drivers
    • ADC
      • ADC_Private_Macros
        • ADC_REGISTER_BIT_DEFINITIONS
      • ADC_Public_Types
      • ADC_Public_Functions
    • CAN
      • CAN_Private_Macros
        • CAN_REGISTER_BIT_DEFINITION
      • CAN_Public_Types
      • CAN_Public_Macros
      • CAN_Public_Functions
      • CAN_Private_Variables
    • CLKPWR
      • CLKPWR_Private_Macros
        • CLKPPWR_REGISTER_BIT_DEFINITIONS
      • CLKPWR_Public_Macros
      • CLKPWR_Public_Functions
    • DAC
      • DAC_Public_Types
      • DAC_Public_Macros
      • DAC_Public_Functions
    • EMAC
      • EMAC_Private_Macros
        • EMAC_REGISTER_BIT_DEFINITIONS
      • EMAC_Public_Types
      • EMAC_Public_Macros
      • EMAC_Public_Functions
      • EMAC_Private_Variables
      • EMAC_Private_Functions
    • GPDMA
      • GPDMA_Private_Macros
        • DMA_REGISTER_BIT_DEFINITIONS
      • GPDMA_Public_Types
      • GPDMA_Public_Macros
      • GPDMA_Public_Functions
      • GPDMA_Private_Variables
    • GPIO
      • GPIO_Public_Types
      • GPIO_Public_Macros
      • GPIO_Public_Functions
      • GPIO_Private_Functions
    • I2C
      • I2C_Private_Macros
        • I2C_REGISTER_BIT_DEFINITIONS
      • I2C_Public_Types
      • I2C_Public_Macros
      • I2C_Public_Functions
      • I2C_Private_Types
      • I2C_Private_Functions
    • I2S
      • I2S_Private_Macros
        • I2S_REGISTER_BIT_DEFINITION
      • I2S_Public_Types
      • I2S_Public_Macros
      • I2S_Public_Functions
      • I2S_Private_Functions
    • LIBCFG_DEFAULT
      • LIBCFG_DEFAULT_Public_Macros
      • LIBCFG_DEFAULT_Public_Functions
    • MCPWM
      • MCPWM_Private_Macros
        • MCPWM_REGISTER_BIT_DEFINITIONS
      • MCPWM_Public_Types
      • MCPWM_Public_Macros
      • MCPWM_Public_Functions
    • NVIC
      • NVIC_Public_Functions
      • NVIC_Private_Macros
    • PINSEL
      • PINSEL_Private_Macros
        • PINSEL_REGISTER_BIT_DEFINITIONS
      • PINSEL_Public_Macros
      • PINSEL_Public_Types
      • PINSEL_Public_Functions
    • PWM
      • PWM_Private_Macros
        • PWM_REGISTER_BIT_DEFINITIONS
      • PWM_Public_Types
      • PWM_Public_Functions
    • QEI
      • QEI_Private_Macros
        • QEI_REGISTER_BIT_DEFINITIONS
      • QEI_Public_Types
      • QEI_Public_Macros
      • QEI_Public_Functions
      • QEI_Private_Types
    • RIT
      • RIT_Private_Macros
        • RIT_REGISTER_BIT_DEFINITIONS
      • RIT_Public_Types
      • RIT_Public_Functions
    • RTC
      • RTC_Private_Macros
        • RTC_REGISTER_BIT_DEFINITIONS
      • RTC_Public_Types
      • RTC_Public_Macros
      • RTC_Public_Functions
    • SPI
      • SPI_Private_Macros
        • SPI_REGISTER_BIT_DEFINITION
      • SPI_Public_Types
      • SPI_Public_Macros
      • SPI_Public_Functions
      • SPI_Private_Types
      • SPI_Private_Functions
    • SSP
      • SSP_Private_Macros
        • SSP_REGISTER_BIT_DEFINITION
      • SSP_Public_Types
      • SSP_Public_Macros
      • SSP_Public_Functions
      • SSP_Private_Types
      • SSP_Private_Functions
    • TIM
      • TIM_Private_Macros
        • TIM_REGISTER_BIT_DEFINITION
      • TIM_Public_Types
      • TIM_Public_Macros
      • TIM_Public_Functions
      • TIM_Private_Functions
    • UART
      • UART_Private_Macros
        • UART_REGISTER_BIT_DEFINITIONS
      • UART_Public_Types
      • UART_Public_Macros
      • UART_Public_Functions
      • UART_Private_Types
      • UART_Private_Variables
      • UART_Private_Functions
    • WDT
      • WDT_Private_Macros
        • WDT_REGISTER_BIT_DEFINITIONS
      • WDT_Public_Types
      • WDT_Public_Functions
      • WDT_Private_Functions
    • LPC_Types
      • LPC_Types_Public_Types
      • LPC_Types_Public_Macros
  • CMSIS CM3 Core Lint Configuration
  • CM3 Core Definitions
    • CMSIS CM3 Core Register
      • CMSIS CM3 NVIC
      • CMSIS CM3 SCB
      • CMSIS CM3 SysTick
      • CMSIS CM3 ITM
      • CMSIS CM3 Interrupt Type
      • CMSIS CM3 Core Debug
    • CMSIS CM3 Core Function Interface
    • CMSIS CM3 Core Debug Interface
• Data Structures
  • AF_SectionDef
  • CAN_MSG_Type
  • CAN_PinCFG_Type
  • CoreDebug_Type
  • DAC_CONVERTER_CFG_Type
  • EFF_Entry
  • EFF_GPR_Entry
  • EMAC_CFG_Type
  • EMAC_PACKETBUF_Type
  • FullCAN_Entry
  • GPDMA_Channel_CFG_Type
  • GPDMA_LLI_Type
  • GPIO_Byte_TypeDef
  • GPIO_HalfWord_TypeDef
  • I2C_CFG_T
  • I2C_M_SETUP_Type
  • I2C_OWNSLAVEADDR_CFG_Type
  • I2C_S_SETUP_Type
  • I2S_CFG_Type
  • I2S_DMAConf_Type
  • I2S_MODEConf_Type
  • I2S_PinCFG_Type
  • InterruptType_Type
  • ITM_Type
  • LPC_ADC_TypeDef
  • LPC_CAN_TypeDef
  • LPC_CANAF_RAM_TypeDef
  • LPC_CANAF_TypeDef
  • LPC_CANCR_TypeDef
  • LPC_DAC_TypeDef
  • LPC_EMAC_TypeDef
  • LPC_GPDMA_TypeDef
  • LPC_GPDMACH_TypeDef
  • LPC_GPIO_TypeDef
  • LPC_GPIOINT_TypeDef
  • LPC_I2C_TypeDef
  • LPC_I2S_TypeDef
  • LPC_MCPWM_TypeDef
  • LPC_PINCON_TypeDef
  • LPC_PWM_TypeDef
  • LPC_QEI_TypeDef
  • LPC_RIT_TypeDef
  • LPC_RTC_TypeDef
  • LPC_SC_TypeDef
  • LPC_SPI_TypeDef
  • LPC_SSP_TypeDef
  • LPC_TIM_TypeDef
  • LPC_UART0_TypeDef
  • LPC_UART1_TypeDef
  • LPC_UART_TypeDef
  • LPC_USB_TypeDef
  • LPC_WDT_TypeDef
  • MCPWM_CAPTURE_CFG_Type
  • MCPWM_CHANNEL_CFG_Type
  • MCPWM_COUNT_CFG_Type
  • NVIC_Type
  • PINSEL_CFG_Type
  • PWM_CAPTURECFG_Type
  • PWM_COUNTERCFG_Type
  • PWM_MATCHCFG_Type
  • PWM_TIMERCFG_Type
  • QEI_CFG_Type
  • QEI_CFGOPT_Type
  • QEI_RELOADCFG_Type
  • RIT_CMP_VAL
  • RTC_TIME_Type
  • RX_Desc
  • RX_Stat
  • SCB_Type
  • SFF_Entry
  • SFF_GPR_Entry
  • SPI_CFG_T
  • SPI_CFG_Type
  • SPI_DATA_SETUP_Type
  • SSP_CFG_T
  • SSP_CFG_Type
  • SSP_DATA_SETUP_Type
  • SysTick_Type
  • TIM_CAPTURECFG_Type
  • TIM_COUNTERCFG_Type
  • TIM_MATCHCFG_Type
  • TIM_TIMERCFG_Type
  • TX_Desc
  • TX_Stat
  • UART1_RS485_CTRLCFG_Type
  • UART_AB_CFG_Type
  • UART_CBS_Type
  • UART_CFG_Type
  • UART_FIFO_CFG_Type
• Data Fields
• File List
  • C:/nxpdrv/LPC1700CMSIS/_htmlsrc/ummainpage.h
  • C:/nxpdrv/LPC1700CMSIS/Core/CM3/CoreSupport/core_cm3.c
  • C:/nxpdrv/LPC1700CMSIS/Core/CM3/CoreSupport/core_cm3.h
  • C:/nxpdrv/LPC1700CMSIS/Core/CM3/DeviceSupport/NXP/LPC17xx/LPC17xx.h
  • C:/nxpdrv/LPC1700CMSIS/Core/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c
  • C:/nxpdrv/LPC1700CMSIS/Core/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_adc.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_can.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_clkpwr.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_dac.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_emac.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_gpdma.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_gpio.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_i2c.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_i2s.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_libcfg_default.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_mcpwm.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_nvic.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_pinsel.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_pwm.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_qei.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_rit.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_rtc.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_spi.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_ssp.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_timer.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_uart.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_wdt.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc_types.h
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_adc.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_can.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_clkpwr.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_dac.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_emac.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_gpdma.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_gpio.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_i2c.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_i2s.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_libcfg_default.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_mcpwm.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_nvic.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_pinsel.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_pwm.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_qei.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_rit.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_rtc.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_spi.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_ssp.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_timer.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_uart.c
  • C:/nxpdrv/LPC1700CMSIS/Drivers/source/lpc17xx_wdt.c
• Globals

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