C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_timer.h
Go to the documentation of this file.00001 00020 /* Peripheral group ----------------------------------------------------------- */ 00026 #ifndef __LPC17XX_TIMER_H_ 00027 #define __LPC17XX_TIMER_H_ 00028 00029 /* Includes ------------------------------------------------------------------- */ 00030 #include "LPC17xx.h" 00031 #include "lpc_types.h" 00032 00033 00034 /* Private Macros ------------------------------------------------------------- */ 00039 /************************** TIMER/COUNTER Control **************************/ 00044 /********************************************************************** 00045 ** Interrupt information 00046 **********************************************************************/ 00048 #define TIM_IR_CLR(n) _BIT(n) 00049 00050 /********************************************************************** 00051 ** Timer interrupt register definitions 00052 **********************************************************************/ 00054 #define TIM_MATCH_INT(n) (_BIT(n & 0x0F)) 00055 00056 #define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4))) 00057 00058 /********************************************************************** 00059 * Timer control register definitions 00060 **********************************************************************/ 00062 #define TIM_ENABLE ((uint32_t)(1<<0)) 00063 00064 #define TIM_RESET ((uint32_t)(1<<1)) 00065 00066 #define TIM_TCR_MASKBIT ((uint32_t)(3)) 00067 00068 /********************************************************************** 00069 * Timer match control register definitions 00070 **********************************************************************/ 00072 #define TIM_INT_ON_MATCH(n) (_BIT((n * 3))) 00073 00074 #define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1))) 00075 00076 #define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2))) 00077 00078 #define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF)) 00079 00080 #define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<n)) 00081 /********************************************************************** 00082 * Timer capture control register definitions 00083 **********************************************************************/ 00085 #define TIM_CAP_RISING(n) (_BIT((n * 3))) 00086 00087 #define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1))) 00088 00089 #define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2))) 00090 00091 #define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03)) 00092 00093 #define TIM_CCR_MASKBIT ((uint32_t)(0x3F)) 00094 00095 #define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<n)) 00096 00097 /********************************************************************** 00098 * Timer external match register definitions 00099 **********************************************************************/ 00102 #define TIM_EM(n) _BIT(n) 00103 00104 #define TIM_EM_NOTHING ((uint8_t)(0x0)) 00105 00106 #define TIM_EM_LOW ((uint8_t)(0x1)) 00107 00108 #define TIM_EM_HIGH ((uint8_t)(0x2)) 00109 00110 #define TIM_EM_TOGGLE ((uint8_t)(0x3)) 00111 00112 #define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03))) 00113 00114 #define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03)) 00115 00116 #define TIM_EMR_MASKBIT 0x0FFF 00117 /********************************************************************** 00118 * Timer Count Control Register definitions 00119 **********************************************************************/ 00121 #define TIM_CTCR_MODE_MASK 0x3 00122 00123 #define TIM_CTCR_INPUT_MASK 0xC 00124 00125 #define TIM_CTCR_MASKBIT 0xF 00126 #define TIM_COUNTER_MODE ((uint8_t)(1)) 00127 00137 /* Public Types --------------------------------------------------------------- */ 00142 /*********************************************************************** 00143 * Timer device enumeration 00144 **********************************************************************/ 00146 typedef enum 00147 { 00148 TIM_MR0_INT =0, 00149 TIM_MR1_INT =1, 00150 TIM_MR2_INT =2, 00151 TIM_MR3_INT =3, 00152 TIM_CR0_INT =4, 00153 TIM_CR1_INT =5, 00154 }TIM_INT_TYPE; 00155 #define PARAM_TIM_INT_TYPE(TYPE) ((TYPE ==TIM_MR0_INT)||(TYPE ==TIM_MR1_INT)\ 00156 ||(TYPE ==TIM_MR2_INT)||(TYPE ==TIM_MR3_INT)\ 00157 ||(TYPE ==TIM_CR0_INT)||(TYPE ==TIM_CR1_INT)) 00158 00160 typedef enum 00161 { 00162 TIM_TIMER_MODE = 0, 00163 TIM_COUNTER_RISING_MODE, 00164 TIM_COUNTER_FALLING_MODE, 00165 TIM_COUNTER_ANY_MODE 00166 } TIM_MODE_OPT; 00167 #define PARAM_TIM_MODE_OPT(MODE) ((MODE == TIM_TIMER_MODE)||(MODE == TIM_COUNTER_RISING_MODE)\ 00168 || (MODE == TIM_COUNTER_RISING_MODE)||(MODE == TIM_COUNTER_RISING_MODE)) 00169 00170 typedef enum 00171 { 00172 TIM_PRESCALE_TICKVAL = 0, 00173 TIM_PRESCALE_USVAL 00174 } TIM_PRESCALE_OPT; 00175 #define PARAM_TIM_PRESCALE_OPT(OPT) ((OPT == TIM_PRESCALE_TICKVAL)||(OPT == TIM_PRESCALE_USVAL)) 00176 00177 typedef enum 00178 { 00179 TIM_COUNTER_INCAP0 = 0, 00180 TIM_COUNTER_INCAP1, 00181 } TIM_COUNTER_INPUT_OPT; 00182 #define PARAM_TIM_COUNTER_INPUT_OPT(OPT) ((OPT == TIM_COUNTER_INCAP0)||(OPT == TIM_COUNTER_INCAP1)) 00183 00185 typedef enum 00186 { 00187 TIM_EXTMATCH_NOTHING = 0, 00188 TIM_EXTMATCH_LOW, 00189 TIM_EXTMATCH_HIGH, 00190 TIM_EXTMATCH_TOGGLE 00191 }TIM_EXTMATCH_OPT; 00192 #define PARAM_TIM_EXTMATCH_OPT(OPT) ((OPT == TIM_EXTMATCH_NOTHING)||(OPT == TIM_EXTMATCH_LOW)\ 00193 ||(OPT == TIM_EXTMATCH_HIGH)||(OPT == TIM_EXTMATCH_TOGGLE)) 00194 00196 typedef enum { 00197 TIM_CAPTURE_NONE = 0, 00198 TIM_CAPTURE_RISING, 00199 TIM_CAPTURE_FALLING, 00200 TIM_CAPTURE_ANY 00201 } TIM_CAP_MODE_OPT; 00202 00203 #define PARAM_TIM_CAP_MODE_OPT(OPT) ((OPT == TIM_CAPTURE_NONE)||(OPT == TIM_CAPTURE_RISING) \ 00204 ||(OPT == TIM_CAPTURE_FALLING)||(OPT == TIM_CAPTURE_ANY)) 00205 00207 typedef struct 00208 { 00209 00210 uint8_t PrescaleOption; 00214 uint8_t Reserved[3]; 00215 uint32_t PrescaleValue; 00216 } TIM_TIMERCFG_Type; 00217 00219 typedef struct { 00220 00221 uint8_t CounterOption; 00225 uint8_t CountInputSelect; 00226 uint8_t Reserved[2]; 00227 } TIM_COUNTERCFG_Type; 00228 00230 typedef struct { 00231 uint8_t MatchChannel; 00233 uint8_t IntOnMatch; 00237 uint8_t StopOnMatch; 00241 uint8_t ResetOnMatch; 00246 uint8_t ExtMatchOutputType; 00252 uint8_t Reserved[3]; 00253 uint32_t MatchValue; 00254 } TIM_MATCHCFG_Type; 00255 00256 00258 typedef struct { 00259 uint8_t CaptureChannel; 00261 uint8_t RisingEdge; 00265 uint8_t FallingEdge; 00269 uint8_t IntOnCaption; 00274 } TIM_CAPTURECFG_Type; 00275 00281 /* Public Macros -------------------------------------------------------------- */ 00287 #define PARAM_TIMx(n) ((((uint32_t *)n)==((uint32_t *)LPC_TIM0)) || (((uint32_t *)n)==((uint32_t *)LPC_TIM1)) \ 00288 || (((uint32_t *)n)==((uint32_t *)LPC_TIM2)) || (((uint32_t *)n)==((uint32_t *)LPC_TIM3))) 00289 00295 /* Public Functions ----------------------------------------------------------- */ 00300 FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, uint8_t IntFlag); 00301 FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, uint8_t IntFlag); 00302 void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, uint8_t IntFlag); 00303 void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, uint8_t IntFlag); 00304 void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState); 00305 void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx); 00306 void TIM_Init(LPC_TIM_TypeDef *TIMx, uint8_t TimerCounterMode, void *TIM_ConfigStruct); 00307 void TIM_DeInit(LPC_TIM_TypeDef *TIMx); 00308 void TIM_ConfigStructInit(uint8_t TimerCounterMode, void *TIM_ConfigStruct); 00309 void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct); 00310 void TIM_SetMatchExt(LPC_TIM_TypeDef *TIMx,TIM_EXTMATCH_OPT ext_match ); 00311 void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct); 00312 uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, uint8_t CaptureChannel); 00313 00318 #endif /* __LPC17XX_TIMER_H_ */ 00319 00324 /* --------------------------------- End Of File ------------------------------ */
Generated on Mon Feb 8 10:01:37 2010 for LPC1700CMSIS Standard Peripheral Firmware Library by
