C:/nxpdrv/LPC1700CMSIS/Drivers/include/lpc17xx_clkpwr.h
Go to the documentation of this file.00001 /***********************************************************************/ 00021 /* Peripheral group ----------------------------------------------------------- */ 00027 #ifndef LPC17XX_CLKPWR_H_ 00028 #define LPC17XX_CLKPWR_H_ 00029 00030 /* Includes ------------------------------------------------------------------- */ 00031 #include "lpc17xx.h" 00032 #include "lpc_types.h" 00033 00034 #ifdef __cplusplus 00035 extern "C" 00036 { 00037 #endif 00038 00039 00040 /* Private Macros ------------------------------------------------------------- */ 00049 /* Clock source selection multiplexer definition */ 00051 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00)) 00052 00053 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01)) 00054 00055 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02)) 00056 00057 #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03)) 00058 00059 00060 /* Clock Output Configuration register definition */ 00062 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00)) 00063 00064 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01)) 00065 00066 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02)) 00067 00068 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03)) 00069 00070 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04)) 00071 00072 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4)) 00073 00074 #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8)) 00075 00076 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9)) 00077 00078 #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF)) 00079 00080 00081 /* PLL 0 control definition */ 00083 #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01)) 00084 00085 #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02)) 00086 00087 #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03)) 00088 00089 00090 /* PLL 0 Configuration register definition */ 00092 #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF)) 00093 00094 #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000)) 00095 00096 #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF)) 00097 00098 00099 /* PLL 0 status definition */ 00101 #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF)) 00102 00103 #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF)) 00104 00105 #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24)) 00106 00107 #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25)) 00108 00109 #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26)) 00110 00111 00112 /* PLL0 Feed register definition */ 00114 #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF) 00115 00116 00117 /* USB PLL control definition */ 00119 #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01)) 00120 00121 #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02)) 00122 00123 #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03)) 00124 00125 00126 /* USB PLL configuration definition */ 00128 #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F)) 00129 00130 #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5)) 00131 00132 #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F)) 00133 00134 00135 /* USB PLL status definition */ 00137 #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F)) 00138 00139 #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03)) 00140 00141 #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8)) 00142 00143 #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9)) 00144 00145 #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10)) 00146 00147 00148 /* PLL1 Feed register definition */ 00150 #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF) 00151 00152 00153 /* CPU Clock Configuration register definition */ 00155 #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF)) 00156 00157 /* USB Clock Configuration register definition */ 00159 #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F)) 00160 00161 /* IRC Trim register definition */ 00163 #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F)) 00164 00165 00166 /* Peripheral clock divider bit position definition */ 00168 #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF)) 00169 00170 #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3)) 00171 00172 00176 #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n) 00177 00178 #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03) 00179 00180 #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03)) 00181 00182 00183 /* Power Mode Control register definition */ 00185 #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0)) 00186 00187 #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1)) 00188 00189 #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2)) 00190 00191 #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3)) 00192 00193 #define CLKPWR_PCON_BORD ((uint32_t)(1<<4)) 00194 00195 #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8)) 00196 00197 #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9)) 00198 00199 #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10)) 00200 00201 #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11)) 00202 00203 00205 #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE 00206 00216 /* Public Macros -------------------------------------------------------------- */ 00221 /********************************************************************** 00222 * Peripheral Clock Selection Definitions 00223 **********************************************************************/ 00225 #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0)) 00226 00227 #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2)) 00228 00229 #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4)) 00230 00231 #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6)) 00232 00233 #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8)) 00234 00235 #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12)) 00236 00237 #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14)) 00238 00239 #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16)) 00240 00241 #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20)) 00242 00243 #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22)) 00244 00245 #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24)) 00246 00247 #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26)) 00248 00249 #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28)) 00250 00251 #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30)) 00252 00253 #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32)) 00254 00255 #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36)) 00256 00257 #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38)) 00258 00259 #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42)) 00260 00261 #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44)) 00262 00263 #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46)) 00264 00265 #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48)) 00266 00267 #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50)) 00268 00269 #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52)) 00270 00271 #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54)) 00272 00273 #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58)) 00274 00275 #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60)) 00276 00277 #define CLKPWR_PCLKSEL_MC ((uint32_t)(62)) 00278 00283 /* Peripheral clock divider is set to 4 from CCLK */ 00284 #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0)) 00285 00286 #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1)) 00287 00288 #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2)) 00289 00290 00291 /******************************************************************** 00292 * Power Control for Peripherals Definitions 00293 **********************************************************************/ 00295 #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) 00296 /* Timer/Counter 1 power/clock control bit */ 00297 #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) 00298 00299 #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) 00300 00301 #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) 00302 00303 #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) 00304 00305 #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) 00306 00307 #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8)) 00308 00309 #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) 00310 00311 #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) 00312 00313 #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12)) 00314 00315 #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) 00316 00317 #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) 00318 00319 #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) 00320 00321 #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16)) 00322 00323 #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17)) 00324 00325 #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) 00326 00327 #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) 00328 00329 #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) 00330 00331 #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) 00332 00333 #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) 00334 00335 #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) 00336 00337 #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) 00338 00339 #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) 00340 00341 #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) 00342 00343 #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) 00344 00345 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) 00346 00347 #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) 00348 00349 00355 /* Public Functions ----------------------------------------------------------- */ 00360 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal); 00361 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType); 00362 uint32_t CLKPWR_GetPCLK (uint32_t ClkType); 00363 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState); 00364 void CLKPWR_Sleep(void); 00365 void CLKPWR_DeepSleep(void); 00366 void CLKPWR_PowerDown(void); 00367 void CLKPWR_DeepPowerDown(void); 00368 00374 #ifdef __cplusplus 00375 } 00376 #endif 00377 00378 #endif /* LPC17XX_CLKPWR_H_ */ 00379 00384 /* --------------------------------- End Of File ------------------------------ */
Generated on Mon Feb 8 10:01:36 2010 for LPC1700CMSIS Standard Peripheral Firmware Library by
1.5.9