 |
XMC Peripheral Library for XMC4000 Family
2.1.16
|
#include <xmc_eth_mac.h>
Detailed Description
ETH MAC port control
Field Documentation
| uint32_t __pad0__ |
Reserved bits
| uint32_t __pad1__ |
Reserved bits
| uint32_t clk_rmii |
RMII: Continuous 50 MHz reference clock. MII: Receive clock, 25 MHz for 100Mbit/s, 2.5 MHz for 10Mbit/s (XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t)
| uint32_t clk_tx |
Transmit clock (only MII), 25 MHz for 100Mbit/s, 2.5 MHz for 10Mbit/s (XMC_ETH_MAC_PORT_CTRL_CLK_TX_t)
| uint32_t col |
Collision Detect for only MII (XMC_ETH_MAC_PORT_CTRL_COL_t)
| uint32_t crs |
Carrier sense for only MII (XMC_ETH_MAC_PORT_CTRL_CRS_t)
| uint32_t crs_dv |
RMII: carrier sense/RX_Data valid. MII: RX_Data valid (XMC_ETH_MAC_PORT_CTRL_CRS_DV_t)
| uint32_t mdio |
Bidirectional, push-pull management data I/O line (XMC_ETH_MAC_PORT_CTRL_MDIO_t)
| uint32_t mode |
RMII or MII (XMC_ETH_MAC_PORT_CTRL_MODE_t)
| uint32_t rxd0 |
Receive data bit 0 (XMC_ETH_MAC_PORT_CTRL_RXD0_t)
| uint32_t rxd1 |
Receive data bit 1 (XMC_ETH_MAC_PORT_CTRL_RXD1_t)
| uint32_t rxd2 |
Receive data bit 2 (only MII) (XMC_ETH_MAC_PORT_CTRL_RXD2_t)
| uint32_t rxd3 |
Receive data bit 3 (only MII) (XMC_ETH_MAC_PORT_CTRL_RXD3_t)
| uint32_t rxer |
Receive error (XMC_ETH_MAC_PORT_CTRL_RXER_t)
The documentation for this union was generated from the following file:
Generated on Mon Aug 7 2017 11:33:58 for XMC Peripheral Library for XMC4000 Family by
1.8.11