Data Structures
struct	XMC_I2S_CH_CONFIG_t

Macros
#define	XMC_I2S0_CH0 XMC_USIC0_CH0

#define	XMC_I2S0_CH1 XMC_USIC0_CH1

#define	XMC_I2S1_CH0 XMC_USIC1_CH0

#define	XMC_I2S1_CH1 XMC_USIC1_CH1

#define	XMC_I2S2_CH0 XMC_USIC2_CH0

#define	XMC_I2S2_CH1 XMC_USIC2_CH1

Functions
void	XMC_I2S_CH_ClearStatusFlag (XMC_USIC_CH_t *const channel, const uint32_t flag)

void	XMC_I2S_CH_ConfigureShiftClockOutput (XMC_USIC_CH_t *const channel, const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)

void	XMC_I2S_CH_DisableDataTransmission (XMC_USIC_CH_t *const channel)

void	XMC_I2S_CH_DisableDelayCompensation (XMC_USIC_CH_t *const channel)

void	XMC_I2S_CH_DisableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_I2S_CH_DisableInputInversion (XMC_USIC_CH_t *const channel, const XMC_I2S_CH_INPUT_t input)

void	XMC_I2S_CH_DisableMasterClock (XMC_USIC_CH_t *const channel)

void	XMC_I2S_CH_EnableDataTransmission (XMC_USIC_CH_t *const channel)

void	XMC_I2S_CH_EnableDelayCompensation (XMC_USIC_CH_t *const channel)

void	XMC_I2S_CH_EnableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_I2S_CH_EnableInputInversion (XMC_USIC_CH_t *const channel, const XMC_I2S_CH_INPUT_t input)

void	XMC_I2S_CH_EnableMasterClock (XMC_USIC_CH_t *const channel)

uint16_t	XMC_I2S_CH_GetReceivedData (XMC_USIC_CH_t *const channel)

uint32_t	XMC_I2S_CH_GetStatusFlag (XMC_USIC_CH_t *const channel)

void	XMC_I2S_CH_Init (XMC_USIC_CH_t const channel, const XMC_I2S_CH_CONFIG_t const config)

void	XMC_I2S_CH_Receive (XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CHANNEL_t channel_number)

void	XMC_I2S_CH_SelectInterruptNodePointer (XMC_USIC_CH_t *const channel, const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t interrupt_node, const uint32_t service_request)

XMC_I2S_CH_STATUS_t	XMC_I2S_CH_SetBaudrate (XMC_USIC_CH_t *const channel, const uint32_t rate)

void	XMC_I2S_CH_SetBitOrderLsbFirst (XMC_USIC_CH_t *const channel)

void	XMC_I2S_CH_SetBitOrderMsbFirst (XMC_USIC_CH_t *const channel)

void	XMC_I2S_CH_SetFrameLength (XMC_USIC_CH_t *const channel, const uint8_t frame_length)

void	XMC_I2S_CH_SetInputSource (XMC_USIC_CH_t *const channel, const XMC_I2S_CH_INPUT_t input, const uint8_t source)

void	XMC_I2S_CH_SetInterruptNodePointer (XMC_USIC_CH_t *const channel, const uint8_t service_request)

void	XMC_I2S_CH_SetSystemWordLength (XMC_USIC_CH_t *const channel, uint32_t sclk_cycles_system_word_length)

void	XMC_I2S_CH_SetWordLength (XMC_USIC_CH_t *const channel, const uint8_t word_length)

void	XMC_I2S_CH_Start (XMC_USIC_CH_t *const channel)

XMC_I2S_CH_STATUS_t	XMC_I2S_CH_Stop (XMC_USIC_CH_t *const channel)

void	XMC_I2S_CH_Transmit (XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number)

void	XMC_I2S_CH_TriggerServiceRequest (XMC_USIC_CH_t *const channel, const uint32_t service_request_line)

void	XMC_I2S_CH_WordAddressSignalPolarity (XMC_USIC_CH_t *const channel, const XMC_I2S_CH_WA_POLARITY_t wa_inversion)

Detailed Description

USIC IIS Features:

Macro Definition Documentation

#define XMC_I2S0_CH0 XMC_USIC0_CH0

USIC0 channel 0 base address

#define XMC_I2S0_CH1 XMC_USIC0_CH1

USIC0 channel 1 base address

#define XMC_I2S1_CH0 XMC_USIC1_CH0

USIC1 channel 0 base address

#define XMC_I2S1_CH1 XMC_USIC1_CH1

USIC1 channel 1 base address

#define XMC_I2S2_CH0 XMC_USIC2_CH0

USIC2 channel 0 base address

#define XMC_I2S2_CH1 XMC_USIC2_CH1

USIC2 channel 1 base address

Enumeration Type Documentation

enum XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t

I2S Baudrate Generator shift clock output.

Enumerator
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK	Baudrate Generator shift clock output: SCLK
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1	Clock obtained as input from master: DX1

enum XMC_I2S_CH_BUS_MODE_t

Defines the I2S bus mode.

Enumerator
XMC_I2S_CH_BUS_MODE_MASTER	I2S Master
XMC_I2S_CH_BUS_MODE_SLAVE	I2S Slave

enum XMC_I2S_CH_CHANNEL_t

Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal.

Enumerator
XMC_I2S_CH_CHANNEL_1_LEFT	Channel 1 (left)
XMC_I2S_CH_CHANNEL_2_RIGHT	Channel 2 (right)

enum XMC_I2S_CH_EVENT_t

I2S events.

Enumerator
XMC_I2S_CH_EVENT_RECEIVE_START	Receive start event
XMC_I2S_CH_EVENT_DATA_LOST	Data lost event
XMC_I2S_CH_EVENT_TRANSMIT_SHIFT	Transmit shift event
XMC_I2S_CH_EVENT_TRANSMIT_BUFFER	Transmit buffer event
XMC_I2S_CH_EVENT_STANDARD_RECEIVE	Receive event
XMC_I2S_CH_EVENT_ALTERNATIVE_RECEIVE	Alternate receive event
XMC_I2S_CH_EVENT_BAUD_RATE_GENERATOR	Baudrate generator event
XMC_I2S_CH_EVENT_WA_FALLING_EDGE	WA falling edge event
XMC_I2S_CH_EVENT_WA_RISING_EDGE	WA rising edge event
XMC_I2S_CH_EVENT_WA_GENERATION_END	END event
XMC_I2S_CH_EVENT_DX2TIEN_ACTIVATED	WA input signal transition event

enum XMC_I2S_CH_INPUT_t

I2S input stage selection.

Enumerator
XMC_I2S_CH_INPUT_DIN0	Data input stage 0
XMC_I2S_CH_INPUT_SLAVE_SCLKIN	Clock input stage
XMC_I2S_CH_INPUT_SLAVE_WA	WA input stage
XMC_I2S_CH_INPUT_DIN1	Data input stage 1
XMC_I2S_CH_INPUT_DIN2	Data input stage 2
XMC_I2S_CH_INPUT_DIN3	Data input stage 3

enum XMC_I2S_CH_INTERRUPT_NODE_POINTER_t

I2S channel interrupt node pointers.

Enumerator
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT	Node pointer for transmit shift interrupt
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER	Node pointer for transmit buffer interrupt
XMC_I2S_CH_INTERRUPT_NODE_POINTER_RECEIVE	Node pointer for receive interrupt
XMC_I2S_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE	Node pointer for alternate receive interrupt
XMC_I2S_CH_INTERRUPT_NODE_POINTER_PROTOCOL	Node pointer for protocol related interrupts

enum XMC_I2S_CH_STATUS_FLAG_t

I2S status flag.

Enumerator
XMC_I2S_CH_STATUS_FLAG_WORD_ADDRESS	Word Address status
XMC_I2S_CH_STATUS_FLAG_DX2S	Status of WA input(DX2) signal
XMC_I2S_CH_STATUS_FLAG_DX2T_EVENT_DETECTED	Status for WA input signal transition
XMC_I2S_CH_STATUS_FLAG_WA_FALLING_EDGE_EVENT	Falling edge of the WA output signal has been generated
XMC_I2S_CH_STATUS_FLAG_WA_RISING_EDGE_EVENT	Rising edge of the WA output signal has been generated
XMC_I2S_CH_STATUS_FLAG_WA_GENERATION_END	The WA generation has ended
XMC_I2S_CH_STATUS_FLAG_RECEIVER_START_INDICATION	Receive start indication status
XMC_I2S_CH_STATUS_FLAG_DATA_LOST_INDICATION	Data lost indication status
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION	Transmit shift indication status
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION	Transmit buffer indication status
XMC_I2S_CH_STATUS_FLAG_RECEIVE_INDICATION	Receive indication status
XMC_I2S_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION	Alternate receive indication status
XMC_I2S_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION	Baud rate generator indication status

enum XMC_I2S_CH_STATUS_t

I2S Status.

Enumerator
XMC_I2S_CH_STATUS_OK	Status OK
XMC_I2S_CH_STATUS_ERROR	Status ERROR
XMC_I2S_CH_STATUS_BUSY	Status BUSY

enum XMC_I2S_CH_WA_POLARITY_t

Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal.

Enumerator
XMC_I2S_CH_WA_POLARITY_DIRECT	The SELO outputs have the same polarity as the WA signal (active high)
XMC_I2S_CH_WA_POLARITY_INVERTED	The SELO outputs have the inverted polarity to the WA signal (active low)

Function Documentation

void XMC_I2S_CH_ClearStatusFlag	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	flag
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
flag	Protocol event status to be cleared for detection of next occurence. Refer @ XMC_I2S_CH_STATUS_FLAG_t for valid values. OR combinations of these enum item can be used as input.

Returns: None

Description:: Clears the events specified, by setting PSCR register.

During communication the events occurred have to be cleared to detect their next occurence.
e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized.

Related APIs:: XMC_I2S_CH_GetStatusFlag()

void XMC_I2S_CH_ConfigureShiftClockOutput	(	XMC_USIC_CH_t *const	channel,
		const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t	clock_output
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
clock_output	shift clock source. Refer XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs.

Returns: None

Description:: Configures the shift clock source by setting BRG.SCLKOSEL.

In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available for external slave devices by SCLKOUT signal.
In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.

void XMC_I2S_CH_DisableDataTransmission ( XMC_USIC_CH_t *const channel )

Parameters

channel Constant pointer to USIC channel handle of type XMC_USIC_CH_t
Range: XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0,XMC_I2S1_CH1,XMC_I2S2_CH0,XMC_I2S2_CH1

Note: Availability of I2S1 and I2S2 depends on device selection

Returns: None

Description: Disable data transmission.

Use this function in combination with XMC_I2S_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().

Related APIs:: XMC_I2S_CH_EnableDataTransmission()

void XMC_I2S_CH_DisableDelayCompensation ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0,XMC_I2S1_CH1,XMC_I2S2_CH0,XMC_I2S2_CH1

Note: Availability of I2S1 and I2S2 depends on device selection

Returns: None

Description: Disables delay compensation..

Related APIs:: XMC_I2S_CH_EnableDelayCompensation()

void XMC_I2S_CH_DisableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
event	Protocol events which have to be disabled. Refer @ XMC_I2S_CH_EVENT_t for valid values. OR combinations of these enum item can be used as input.

Returns: None

Description:: Disables the I2S protocol specific events, by configuring PCR register.

After disabling the events, XMC_I2S_CH_EnableEvent() has to be invoked to re-enable the events.

Related APIs:: XMC_I2S_CH_EnableEvent()

void XMC_I2S_CH_DisableInputInversion	(	XMC_USIC_CH_t *const	channel,
		const XMC_I2S_CH_INPUT_t	input
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
input	I2S channel input stage. Refer XMC_I2S_CH_INPUT_t for valid inputs.

Returns: None

Description: Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = input).

Resets the input data polarity. Invoke XMC_I2S_CH_EnableInputInversion() to apply inversion.

Related APIs:: XMC_I2S_CH_EnableInputInversion()

void XMC_I2S_CH_DisableMasterClock ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Disables the generation of Master clock by clearing PCR.MCLK bit.

This clock can be enabled by invoking XMC_I2S_CH_EnableMasterClock() as needed in the program.

Related APIs:: XMC_I2S_CH_EnableMasterClock()

void XMC_I2S_CH_EnableDataTransmission ( XMC_USIC_CH_t *const channel )

Parameters

channel Constant pointer to USIC channel handle of type XMC_USIC_CH_t
Range: XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0,XMC_I2S1_CH1,XMC_I2S2_CH0,XMC_I2S2_CH1

Note: Availability of I2S1 and I2S2 depends on device selection

Returns: None

Description: Enable data transmission.

Use this function in combination with XMC_I2S_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().

Note: If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()

Related APIs:: XMC_I2S_CH_DisableDataTransmission()

void XMC_I2S_CH_EnableDelayCompensation ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0,XMC_I2S1_CH1,XMC_I2S2_CH0,XMC_I2S2_CH1

Note: Availability of I2S1 and I2S2 depends on device selection

Returns: None

Description: Enables delay compensation.

Delay compensation can be applied to the receive path.

Related APIs:: XMC_I2S_CH_DisableDelayCompensation()

void XMC_I2S_CH_EnableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
event	Protocol events which have to be enabled. Refer @ XMC_I2S_CH_EVENT_t for valid values. OR combinations of these enum items can be used as input.

Returns: None

Description:: Enables the I2S protocol specific events, by configuring PCR register.

Events can be enabled as needed using XMC_I2S_CH_EnableEvent(). XMC_I2S_CH_DisableEvent() can be used to disable the events.

Related APIs:: XMC_I2S_CH_DisableEvent()

void XMC_I2S_CH_EnableInputInversion	(	XMC_USIC_CH_t *const	channel,
		const XMC_I2S_CH_INPUT_t	input
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
input	I2S channel input stage. Refer XMC_I2S_CH_INPUT_t for valid inputs.

Returns: None

Description: Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = input).

This is not set in XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableInputInversion() as needed later in the program. To disable the inversion XMC_I2S_CH_DisableInputInversion() can be invoked.

Related APIs:: XMC_I2S_CH_DisableInputInversion()

void XMC_I2S_CH_EnableMasterClock ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Enables the generation of Master clock by setting PCR.MCLK bit.

This clock can be used as a clock reference for external devices. This is not enabled during initialization in XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by XMC_I2S_CH_DisableMasterClock().

Related APIs:: XMC_I2S_CH_DisableMasterClock()

uint16_t XMC_I2S_CH_GetReceivedData ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: uint16_t Data read from the receive buffer.

Description:: Reads data from the receive buffer based on the FIFO selection.

Invocation of XMC_I2S_CH_Receive() receives the data and place it into receive buffer. After receiving the data XMC_I2S_CH_GetReceivedData() can be used to read the data from the buffer.

Related APIs:: XMC_I2S_CH_Receive()

uint32_t XMC_I2S_CH_GetStatusFlag ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: uint32_t Status of I2S protocol events.

Description:: Returns the status of the events, by reading PSR register.

This indicates the status of the all the events, for I2S communication.

Related APIs:: XMC_I2S_CH_ClearStatusFlag()

void XMC_I2S_CH_Init	(	XMC_USIC_CH_t *const	channel,
		const XMC_I2S_CH_CONFIG_t *const	config
	)

Parameters

channel Constant pointer to USIC channel handle of type XMC_USIC_CH_t
Range: XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0, XMC_I2S1_CH1,XMC_I2S2_CH0, XMC_I2S2_CH1

Note: Availability of I2S1 and I2S2 depends on device selection

Parameters

config Constant pointer to I2S configuration structure of type XMC_I2S_CH_CONFIG_t.

Returns: XMC_I2S_CH_STATUS_t Status of initializing the USIC channel for I2S protocol.
Range: XMC_I2S_CH_STATUS_OK if initialization is successful.
XMC_I2S_CH_STATUS_ERROR if configuration of baudrate failed.

Description: Initializes the USIC channel for I2S protocol.

During the initialization, USIC channel is enabled and baudrate is configured. After each change of the WA signal, a complete data frame is intended to be transferred (frame length <= system word length). The number of data bits transferred after a change of signal WA is defined by config->frame_length. A data frame can consist of several data words with a data word length defined by config->data_bits. The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA. The system word length is set by default to the frame length defined by config->frame_length.

XMC_I2S_CH_Start() should be invoked after the initialization to enable the channel.

Related APIs:: XMC_I2S_CH_Start(), XMC_I2S_CH_Stop(), XMC_I2S_CH_Transmit(), XMC_I2S_CH_SetSystemWordLength()

void XMC_I2S_CH_Receive	(	XMC_USIC_CH_t *const	channel,
		const XMC_I2S_CH_CHANNEL_t	channel_number
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
channel_number	Communication output channel of the I2S, based on this mode TCI(Transmit control information)is updated. Refer XMC_I2S_CH_CHANNEL_t for valid values.

Returns: None

Description:: Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.

XMC_I2S_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data XMC_I2S_CH_GetReceivedData() can be invoked to read the data from the buffers.

Related APIs:: XMC_I2S_CH_GetReceivedData()

void XMC_I2S_CH_SelectInterruptNodePointer	(	XMC_USIC_CH_t *const	channel,
		const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t	interrupt_node,
		const uint32_t	service_request
	)

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0,XMC_I2S1_CH1,XMC_I2S2_CH0,XMC_I2S2_CH1

Note: Availability of I2S1 and I2S2 depends on device selection

Parameters

interrupt_node	Interrupt node pointer to be configured. Range: XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
service_request	Service request number. Range: 0 to 5.

Returns: None

Description: Sets the interrupt node for USIC channel events.

For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). The NVIC node gets linked to the interrupt event by doing so.
Note: NVIC node should be separately enabled to generate the interrupt.

Related APIs:: XMC_I2S_CH_EnableEvent()

XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	rate
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
rate	Bus speed in bits per second

Returns: XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for setting baudrate is processed.
XMC_I2S_CH_STATUS_OK- If the baudrate is successfully changed.
XMC_I2S_CH_STATUS_ERROR- If the new baudrate value is out of range.

Description:: Sets the bus speed in bits per second

Related APIs:: XMC_I2S_CH_Init(), XMC_I2S_CH_Stop()

void XMC_I2S_CH_SetBitOrderLsbFirst ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.

This is typically based on the slave settings. Invoke XMC_I2S_CH_SetBitOrderLsbFirst() to set direction as needed in the program.

Related APIs:: XMC_I2S_CH_SetBitOrderMsbFirst()

void XMC_I2S_CH_SetBitOrderMsbFirst ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.

This is typically based on the slave settings. This is not set during XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_SetBitOrderMsbFirst() to set direction as needed in the program.

Related APIs:: XMC_I2S_CH_SetBitOrderLsbFirst()

void XMC_I2S_CH_SetFrameLength	(	XMC_USIC_CH_t *const	channel,
		const uint8_t	frame_length
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
frame_length	Number of bits in a frame. Range: 1 to 64.

Returns: None

Description: Define the data frame length.

Set the number of bits to be serially transmitted in a frame. The frame length should be multiples of word length.

Related APIs:: XMC_USIC_CH_SetWordLength()

void XMC_I2S_CH_SetInputSource	(	XMC_USIC_CH_t *const	channel,
		const XMC_I2S_CH_INPUT_t	input,
		const uint8_t	source
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
input	I2S channel input stage. Refer XMC_I2S_CH_INPUT_t for valid values
source	Input source select for the input stage. Range : [0 to 7]

Returns: None

Description: Selects the data source for I2S input stage, by configuring DXCR.DSEL bits.

Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting the I2S communication.

void XMC_I2S_CH_SetInterruptNodePointer	(	XMC_USIC_CH_t *const	channel,
		const uint8_t	service_request
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
service_request	Service request number. Range: [0 to 5]

Returns: None

Description: Sets the interrupt node for I2S channel events.

For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_I2S_CH_Init() during initialization.

Note::

NVIC node should be separately enabled to generate the interrupt.

Related APIs:: XMC_USIC_CH_EnableEvent()

void XMC_I2S_CH_SetSystemWordLength	(	XMC_USIC_CH_t *const	channel,
		uint32_t	sclk_cycles_system_word_length
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
sclk_cycles_system_word_length	system word length in terms of sclk clock cycles.

Returns: None

Description:: Configures the system word length by setting BRG.DCTQ bit field.

This value has to be always higher than 1U and lower than the data with (SCTR.FLE)

void XMC_I2S_CH_SetWordLength	(	XMC_USIC_CH_t *const	channel,
		const uint8_t	word_length
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
word_length	Number of bits to be configured for a data word. Range: 1 to 16.

Returns: None

Description: Defines the data word length.

Sets the number of bits to represent a data word. Frame length should be a multiple of word length.

Related APIs:: XMC_I2S_CH_SetFrameLength()

void XMC_I2S_CH_Start ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Set the selected USIC channel to operate in I2S mode, by setting CCR.MODE bits.

It should be executed after XMC_I2S_CH_Init() during initialization. By invoking XMC_I2S_CH_Stop(), the MODE is set to IDLE state. Call XMC_I2S_CH_Start() to set the I2S mode again, as needed later in the program.

Related APIs:: XMC_I2S_CH_Init(), XMC_I2S_CH_Stop()

XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for stopping is processed.
XMC_I2S_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode.
XMC_I2S_CH_STATUS_BUSY- If the USIC channel is busy transmitting data.

Description:: Set the selected I2S channel to IDLE mode, by clearing CCR.MODE bits.

After calling XMC_I2S_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_I2S_CH_Start() has to be invoked to start the communication again.

Related APIs:: XMC_I2S_CH_Start()

void XMC_I2S_CH_Transmit	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	data,
		const XMC_I2S_CH_CHANNEL_t	channel_number
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
data	Data to be transmitted
channel_number	Communication output channel of the I2S, based on this channel selection TCI(Transmit control information)is updated. Refer XMC_I2S_CH_CHANNEL_t for valid values.

Returns: None

Description:: Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.

TCI(Transmit Control Information) allows dynamic control of output channel during data transfers. To support this auto update, TCSR.WAMD(Automatic WA mode) will be enabled during the initialization using XMC_I2S_CH_Init() for all modes.

Related APIs:: XMC_I2S_CH_Receive()

void XMC_I2S_CH_TriggerServiceRequest	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	service_request_line
	)

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0,XMC_I2S1_CH1,XMC_I2S2_CH0,XMC_I2S2_CH1

Note: Availability of I2S1 and I2S2 depends on device selection

Parameters

service_request_line service request number of the event to be triggered.
Range: 0 to 5.

Returns: None

Description: Trigger a I2S interrupt service request.

When the I2S service request is triggered, the NVIC interrupt associated with it will be generated if enabled.

Related APIs:: XMC_I2S_CH_SelectInterruptNodePointer()

void XMC_I2S_CH_WordAddressSignalPolarity	(	XMC_USIC_CH_t *const	channel,
		const XMC_I2S_CH_WA_POLARITY_t	wa_inversion
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
wa_inversion	Polarity of the word address signal. Refer XMC_I2S_CH_WA_POLARITY_t for valid values

Returns: None

Description: Set the polarity of the word address signal, by configuring PCR.SELINV bit.

Normally WA signal is active low level signal. This is configured in XMC_I2S_CH_Init() during initialization. Invoke XMC_I2S_CH_WordAddressSignalPolarity() with desired settings as needed later in the program.

XMC Peripheral Library for XMC4000 Family: I2S

XMC Peripheral Library for XMC4000 Family

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